JPH08212178A - Parallel computer - Google Patents

Abstract

PURPOSE: To reduce the overhead of accesses by issuing a single network command for the requests of accesses to be given to plural discontinuous data on the addresses of other processing units(PU) and then having the automatic accesses to these data by means of hardware. CONSTITUTION: In a write command mode, the addresses included in the even- numbered words are outputted to an address bus 160 and the data included in the odd-numbered words are outputted to a data bus 161. Then these addresses and data are written in a main storage 120. Thereby, the writing operations can be requested by a single network command to the discontinuous addresses of the main storage 120. In a read command mode, the addresses included in the even-numbered words are outputted to the bus 160 and an access is given to the storage 120. Then these addresses are paired with the return destination addresses included in the odd-numbered words of a request command, and a remote write command is acquired by a selector 141 and a header assembly circuit 140. This write command is sent back to a requester PU which processes the received command as a write command.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a data transfer system in a parallel computer composed of a plurality of processing units.

[0002]

2. Description of the Related Art A parallel computer in which a large number of processing units (hereinafter, referred to as PUs) are operated in parallel is regarded as promising for dramatically improving computer performance. In a parallel computer, it is important to communicate data efficiently between a large number of PUs, especially in a large-scale numerical operation, in order to transfer a large amount of data required for calculation collectively between the PUs at high speed. Architecture is required.

As a data transfer mechanism in a conventional parallel computer, as shown in Japanese Patent Application Laid-Open No. 6-19856, a mechanism for collectively transferring data of consecutive addresses has been adopted. Each PU has a mechanism for performing DMA with the main memory of another PU, and when the area of the data to be transferred is designated, the hardware of the DMA mechanism automatically transfers the designated area.

[0004]

The above-mentioned conventional technique is effective when all the data to be transferred exists at consecutive addresses (or a fixed pattern such as stride access), but the address of the data to be transferred is effective. However, in the case of random addresses that are not continuous, there is a problem of poor efficiency.

For example, consider the case where writing is performed in a remote non-continuous area. In that case, in the conventional DMA data transfer mechanism that can only write to consecutive addresses,
Multiple data cannot be written in the memory of the other party at once. Therefore, (1) a remote write command is issued for each word. (2) After temporarily transferring the two arrays containing the data to be written and the address to be written to different areas of the destination PU in two steps, the actual data to the area to be originally written to the destination PU is actually transferred to the destination PU. Request write processing. And so on.

In the method (1), a large number of write commands for each word must be sent, so that not only the execution time increases, but also a large number of packets need to be sent out on the network, which imposes a load on the network. Increasing and problematic.

In the method (2), the load on the network is reduced, but a new area for temporarily landing the address and data is newly required, and the efficiency of memory use decreases. Further, since the PU of the other party generates extra work, there is a problem that the execution time of the program increases.

Even when trying to read data at non-contiguous addresses of a remote PU, (1) reading data word by word (2) requesting the other party's CPU to collect data in a continuous area After that, it is necessary to perform processing such as batch transfer, which causes a significant decrease in processing efficiency as in the case of writing.

In particular, in recent years, many programs that use list vectors as a data structure have been found to handle atypical data. In the case of list vector access, since the access destination address is indicated by an array of pointers, data access is generally to non-contiguous addresses. Therefore, in order to execute a list vector program at high speed, a mechanism for transferring data at non-contiguous addresses all at once at high speed is required.

[0010]

In order to achieve the above object, a command structure capable of designating a remote address to be accessed for each data in a network command for transferring a plurality of data. To do.

In the case of writing to non-contiguous addresses of other PUs, a network command sent to a write destination PU has an arbitrary number of sets of write addresses and data to be written. P that received the above command
U distributes the value contained in the address part of each set in the command to the address bus and the value contained in the data part to the data bus, and writes data in the area indicated by the address for the length of the command. repeat. Thus, writing to a plurality of words whose addresses of other PUs are not continuous can be instructed by one command.

In the case of non-consecutive address reading,
Read address in the request command on the network,
A set of addresses in the main memory of the requesting PU to which the read data should be written (hereinafter referred to as a return address) is
Have any number. PU that received the above command
Performs the processing for outputting the value contained in the address portion of each set in the command to the address bus, reading the value in the main memory, and then writing the value in the return destination address. Here, writing the read value to the return destination address is itself writing to a plurality of non-contiguous addresses, so the read value is written using the write command to the non-contiguous addresses described above. To write to the return address. As a result, it is possible to read data of a plurality of words of which addresses are not continuous in another PU and write the data in the area of the own PU.

[0013]

According to the present invention, the main memory access command flowing on the network designates the address of the access destination for each data, and further, the hardware of the responding PU decomposes the command to access the main memory. Provide hardware. As a result, a plurality of data whose addresses in the main memory of another PU are not consecutive can be accessed at high speed with a single network command.

FIG. 1 shows a block diagram of a parallel computer of the present invention. In the figure, reference numeral 130 is a circuit for decomposing the header of a request packet from another PU, and 131 is a circuit for allocating the address and data of the data portion of the request packet. The number of words in the data part is counted by the counter 150.
In the case of a write command, the address contained in the even word is output to the address bus 160, and the data contained in the odd word is output to the data bus 161, and the main memory is written. As a result, writing to non-contiguous addresses in the main memory can be requested by one network command.

In the case of a read command, the address contained in the even word is output to the address bus 160, the main memory is accessed, and the selector 141 is paired with the return destination address contained in the odd word of the request command. Then, the remote writing command is assembled by the header assembling circuit 140 and returned to the requesting PU. At the requesting PU, the other P
Data at non-contiguous addresses of U can be transferred to non-contiguous addresses of its own PU.

A comparator 151 in the figure is a circuit for comparing the number of access words in a command with the value of the counter 150 to detect the end of command processing. As a result, the number of words to be accessed in the packet can be arbitrarily specified, and flexible remote access can be performed.

[0017]

1 to 4 show an embodiment of the present invention.
FIG. 1 is a block diagram of a parallel computer of the present invention. 2 to 4 are formats of command packets in the PU-to-PU network. 2 is a command for designating writing of a plurality of data to non-contiguous addresses (hereinafter referred to as multi-word write), and FIG. 3 is a command for designating reading of a plurality of data of non-contiguous addresses (hereinafter Is called multiword read). On the other hand, FIG. 4 shows a conventional DMA write command (hereinafter referred to as DMA write).

In FIG. 1, 100 and 200 are PU and 9
00 is a network between PUs. In the following, PU100
Only the inside of is described in detail. The other PUs have exactly the same configuration. Inside the PU, 190 is a CPU, 120 is a main memory, 160 is an address bus, 161 is a data bus, 11
Reference numeral 0 is a DMA controller for performing conventional DMA transfer between PUs. Further, 130 is a request command header decomposing circuit for interpreting a header part of a multiword read / multiword write command from another PU, 13
Reference numeral 1 is a switch for allocating the access address of the data part of the request command and the write data (for writing) or the return destination address (for reading). Reference numeral 150 is a counter for counting the number of words in the data section, 150a0 is the least significant bit of the counter, 151 is a comparator for determining the end of the command packet, 132, 1
Reference numeral 33 is a circuit for outputting a main memory access command. A switch 134 switches between multi-word read and multi-word write commands. 140
Is a circuit for assembling a multiword write command header for making a multiword read response, and 141 is for assembling a return destination address and data set in the data part of the multiword write command for making a multiword read response. Is a selector of.

The present invention is characterized in that each PU has a mechanism for separating the address information in the packet by the switch 131 and accessing the main memory in order to execute the multi-word command.

First, the configuration of the entire system will be described. The system executes PU (100,
200) takes the configuration connected by the network. Each PU has a CPU 190 and a main memory 120, and constitutes a main memory distributed multiprocessor system. Communication between PUs is performed by packet communication via a network.

Communication between normal (conventional) PUs is carried out by collectively transferring a certain area on the main memory by means of the 110 DMA communication mechanism.

FIG. 4 shows the format of a DMA write command on the network. A network command has a command name 1001 as a header and a destination PU number 100.
2, a command length (the number of words in the data section) 1003, a transmission source PU number 1004 are placed. The data part is placed after the header part. DMA destination address 1 in the data section
Data sent by DMA 1300d following 300a
~ 1306d is placed. Here, one word of data in this embodiment is 4B. On the DMA transmission side, as shown in FIG.
The CPU creates the packet shown in to the main memory, and DM
The A controller transfers the packet on the main memory to the network. DMA of PU that received DMA write command
The controller sequentially writes the data of DATA0 to DATAn-1 from the area indicated by the start address. D
Since the details of the MA controller are known techniques, the description thereof is omitted here.

Next, the operation of the multi-word write command will be described. FIG. 2 shows the format of the multi-word write command. The header part is the same as the DMA transfer, but the format of the data part is different. In the DMA transfer, there is one transfer destination address specified in the data section, whereas in multiword write, an address is specified for each word of data. In the example in the figure, Da is assigned to the address indicated by Addr0.
It is possible to write each data to different addresses, such as ta0, Addr1 and Data1.

In the PU on the request side of multi-word write,
The CPU creates the packet shown in FIG. 2 in the main memory in advance, and DMA
The controller 110 is used to transfer the packet on the main memory to the network (this part is exactly the same as the DMA write).

The PU receiving the multi-word write sends the packet header to the request command header disassembling circuit 130,
The data part is sent to the switch 131. The request command header disassembling circuit disassembles the header part of the packet and outputs a signal 130d in the case of multiword write according to the command type, and at the same time, the length 130b of the data part and the source P
The U number 130e is output. Word count counter 1
A reset / start signal 130f is sent to 50. Output of counter 150 and length field 130b in packet
Are compared by the comparator 151, and while the two values are different (the counter value is smaller than the packet length), the signal 151a
Is output. At the same time that the counter 150 is enabled by 151a, the write command 133a is transmitted to the main memory 120 by the gate 133.

The switch 131 sets the value 131a of the packet data portion to the address 131c (in the case of an even word) according to the value of the least significant bit 150a0 of the counter, that is, whether the data portion of the packet is an even word or an odd word. Allocate to data 131d (in the case of odd words) (switch 134 is data bus 16 in the case of multi-word write)
Connected to one). As a result, the set of address and data in the packet is transferred to the address bus 160 and the data bus 16
It can be output to 1 and written to the main memory 120.

When the value of the counter 150 becomes equal to the data length 130b of the packet (when the packet ends), 15
The 1a signal is no longer output. As a result, the write signal 133a to the main memory is stopped, the operation of the counter 150 is stopped, and the process ends.

By the above processing, each address and data set in the multi-word write command can be written in the main memory.

Next, the operation of multi-word read will be described. FIG. 3 shows the format of the multi-word read command. The header part is the same as the DMA transfer and the like. The multi-word read is a command for reading the value of an arbitrary address of the other party PU and writing it to an arbitrary address of its own PU. The data section has a plurality of sets of the address of the other party PU to read and the address (return destination address) of the own PU to which the read data is written.

In the example of FIG. 3, the data of the address indicated by Addr0 of the destination PU is read, the data of the address indicated by Dest0 of the own PU is written, and the data of Addr1 is indicated by Dest1.
As described above, it is possible to read data at different addresses of the partner PU and write to different addresses of the own PU.

In the PU on the request side of multi-word read,
The CPU creates the packet of FIG. 3 in the main memory in advance, and DMA
The controller 110 is used to transfer the packet on the main memory to the network.

Upon receiving the multi-word read, the PU sends the packet header to the request command header decomposing circuit 130.
The data part is sent to the switch 131. The request command header decomposing circuit decomposes the header part of the packet, and according to the command type, in the case of multiword read, the signal 130c is generated.
At the same time, the length of the data part 130b and the source PU number 130e are output. Further, a reset / start signal 130f is sent to the word number counter 150. Output of counter 150 and length field 130 in packet
b is compared by the comparator 151, and while the two values are different (the counter value is smaller than the packet length), the signal 151
a is output. The counter 150 is enabled by 151a, and at the same time, the read command 132a is transmitted to the main memory 120 by the gate 132.

The switch 131 determines the value of the packet data portion according to the value of the least significant bit 150a0 of the counter, that is, whether it is an even word or an odd word of the packet data portion.
131a is allocated to an access address 131c (in the case of an even word) and a return destination address 141b (in the case of an odd word) (the switch 134 is connected to the selector 141 in the case of multiword read). After that, the value of the main memory is read using the address on the address bus 160, and the read data is input to the selector 141 via the data bus 161.

Thereafter, the reply command header assembling circuit 14
0, a multi-word write command for returning the read value to the source PU is output using the selector 141. This command writes the values stored in Addr0 to Addrn-1 to Dest0 to Destn-1 of the source PU.

First, the reply command assembling circuit 140 sends the source P sent from the request command header disassembling circuit 130.
The U (that is, reply command destination PU) number 130e and the command length 130b are used to send out the header of the multi-word write command for reply. Data part 141a of packet
The switch 141 is used to set the value of the least significant bit 150a0 of the counter (however, in the reply circuit, one cycle is delayed by using the delay latch 152 to wait for the main memory access), that is, the packet data. Return address 14 depending on whether the part is an even word or an odd word
1b (for even word) or read data 1
41c (in the case of an odd word) is output. This allows
The return destination address sent from the source PU and the set of data read from the main memory can be returned to the source PU as the data part of the multiword write command.

When the value of the counter 150 becomes equal to the data length 130b of the packet (packet ends), 15
The output of the 1a signal is stopped. As a result, the read signal 132a to the main memory is stopped, the operation of the counter 150 is stopped, and the sending of the return command is completed. Through the above processing, the value of each address in the multiword read command can be read and written to the return destination address of the source PU.

By the above method, multi-word write,
By using the multi-word read command, it is possible to collectively perform writing and reading processes for a plurality of words whose addresses in the main memory of another PU are not continuous with one network command.

[0038]

According to the present invention, in a distributed memory type parallel computer, a single network command is used to request access to a plurality of data of non-consecutive addresses in another PU, and the data is automatically executed by hardware. As a result, it becomes possible to significantly reduce the access overhead as compared with the case of using the conventional DMA mechanism that can only access continuous addresses.

[Brief description of drawings]

FIG. 1 is a block diagram of a parallel computer having a remote access mechanism according to an embodiment of the present invention.

FIG. 2 is a diagram showing a format of a multi-word write command on a network.

FIG. 3 is a diagram showing a format of a multiword read command on a network.

FIG. 4 is a diagram showing a format of a conventional DMA write command.

[Explanation of symbols]

100, 200 ... Processing unit, 110 ... D
MA controller, 110a ... DMA command, 120
... main memory, 130 ... decomposition circuit, 130a ... request command header, 130b ... data length, 130c ... multiword read signal, 130d ... multiword write signal, 13
0e ... Source PU number, 130f ... Counter control signal, 131 ... Switch, 131a ... Request command data, 131c ... Main storage address, 131d ... Return destination address, 132 ... Signal output gate, 133 ... Signal output gate, 134 ... Switch Switch, 140 ... Assembly circuit, 140a
... Reply command header, 141 ... Selector, 141a ...
Data, 141b ... Return address, 141c ... Read data, 150 ... Word number counter, 150a ... Counter output, 150a0 ... Counter output least significant bit, 1
51 ... Comparator, 151a ... Command enable signal, 152 ... Latch, 160 ... Address bus, 161 ...
Data bus, 190 ... CPU, 900 ... Network.

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroaki Fujii 1-280, Higashikoigokubo, Kokubunji, Tokyo Inside the Central Research Laboratory, Hitachi, Ltd.

Claims (8)

[Claims] 1. In a parallel computer having a plurality of processing units, each processing unit having an independent main memory, and each processing unit being connected by a network, an address on the main memory of another processing unit. A parallel computer characterized by specifying access to a plurality of non-consecutive data with a single network command. 2. A parallel computer according to claim 1, wherein writing to a plurality of data having arbitrary addresses is requested by the same network command. 3. The parallel computer according to claim 2, wherein the data write command on the network can have an arbitrary number of sets of write addresses and write data. 4. The switch according to claim 3, further comprising a switch for allocating a write address and write data in a write command received from another processing unit to an address line and a data line of the main memory, and writing to the main memory. Parallel computer to do. 5. The parallel computer according to claim 1, wherein reading of a plurality of data having arbitrary addresses is requested by the same network command. 6. A parallel computer according to claim 5, wherein a plurality of data read from another processing unit can be placed at an arbitrary position of a main memory value of its own processing unit. 7. A data read command on a network according to claim 6, wherein an arbitrary number of sets of a read address on the main memory of another processing and an address on the own processing unit for storing the read data can be held. Is a parallel computer. 8. The method according to claim 7, wherein the read address and the address for storing the read data in the read command received from the other processing unit are distributed to the main memory address line and the return destination address of the read data. A parallel computer that has a switch to combine multiple sets of return destination address and read data into one write command and output to the network.