JP4025032B2 - Disk control device and data access method thereof - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a disk controller, and in particular, includes a cache memory unit for storing data to be read from and written to a magnetic disk device, and a shared memory unit for storing control data for the disk controller. The present invention relates to a disk control apparatus having two types of internal memories, which does not require the addition of a shared memory section in response to the addition of a cache memory section.
[0002]
[Prior art]
In today's computer systems, there is a great expectation for improvement in processing performance, and in particular, the demand for improvement in I / O performance of a disk subsystem that uses a magnetic disk, which is a representative auxiliary storage device, as a storage medium is increasing year by year. . The I / O performance of this disk subsystem (hereinafter also referred to as “subsystem”) is about 3 to 4 digits smaller than the I / O performance of the main memory of a computer using a semiconductor storage device as a storage medium. Efforts are being made to reduce this difference, that is, to improve the I / O performance of the subsystem.
[0003]
Also, in large enterprises represented by banks, securities, telephone companies, etc., computer systems and storage systems are configured by centralizing computers and storages that have been distributed in various places in a data center. It tends to reduce the cost of storage system operation, maintenance and management, especially for large / high-end storage systems, support for channel interfaces (connectivity) to connect to hundreds of host computers or more Support for storage capacity of over 100 terabytes is required.
[0004]
As one method for improving the I / O performance of a subsystem, a so-called disk array system is known in which a subsystem is composed of a plurality of magnetic disk devices and data is stored in the plurality of magnetic disk devices. Yes. In the case of a disk array, a plurality of magnetic disk devices that record I / O from a host computer and a disk array controller that accepts I / O of a host computer and transfers it to a plurality of magnetic disk devices (hereinafter simply referred to as “disk control”). It is generally composed of “device”.
[0005]
Such a disk array control device generally has a cache memory unit for storing data read / written to / from the magnetic disk device in the control device in order to improve performance.
[0006]
In addition to such a cache memory unit, there may be a shared memory unit for storing control information for the disk array control device. Such control information includes, for example, cache memory management information in the disk array control device.
[0007]
Hereinafter, the configuration of a disk array control apparatus having two types of internal memories, such as a cache memory unit and a shared memory unit, will be described with reference to FIG.
FIG. 2 is a configuration diagram of a disk array control device in which the internal configuration according to the prior art is a shared bus connection.
[0008]
In the disk array control apparatus 2 shown in FIG. 2, a host IF unit 11, a disk IF unit 12, a shared memory unit 13, and a cache memory unit 14 that are internal components are connected by a shared bus 16.
[0009]
The host IF unit 11 executes data transfer between the host computer 50 and the disk array control device 2, and the disk IF unit 12 is a part that executes data transfer between the magnetic disk device 5 and the disk array control device 2. is there.
[0010]
Further, as described above, the cache memory unit 14 is a memory that temporarily stores data of the magnetic disk device 20, and the shared memory unit 13 is a memory that stores control information related to the disk array control device 2. .
[0011]
In the single disk array control device 2, the shared memory unit 13 and the cache memory unit 14 are configured to be accessible from all the host IF units 11 and the disk IF units 12.
[0012]
The host IF unit 11 has an interface for connecting to the host computer 50 and a microprocessor (not shown) for controlling input / output to the host computer 50. Similarly, the disk IF unit 12 has an interface for connecting to the magnetic disk device 5 and a microprocessor (not shown) for controlling input / output to the magnetic disk device 5. The disk IF unit 12 also executes a RAID function.
[0013]
Each IF unit is connected through an interconnection network using switches instead of the shared bus 16 shown in FIG.
[0014]
[Problems to be solved by the invention]
In the disk array control device, performance is improved by using two types of internal memories depending on the type of data.
[0015]
By the way, the I / O throughput performance of the disk array device is greatly increased, and it is necessary to improve the processing performance of each IF unit in order to cope with it. In the disk array control apparatus according to this prior art, the utilization rate of the shared bus 16 becomes saturated as the processing performance is improved, and thus the throughput performance is limited. Thus, efforts have been made to increase the throughput of the shared bus. However, due to the configuration of the apparatus, it is difficult to improve the bus width, drive frequency, and the like, and there is a limit to improving the throughput.
[0016]
On the other hand, with respect to cache memory, in recent years, the memory capacity has increased with the increase in disk capacity. As the disk device is added, the user may need to add a memory module of the cache memory unit.
[0017]
However, since the shared memory unit stores management information for exclusive control of cache memory access, it is necessary to increase the memory capacity of the shared memory unit by adding a cache memory.
[0018]
Therefore, in the case of the disk array control device according to the above-described prior art, the shared memory unit and the cache memory unit are separated, but in advance according to the peak capacity (maximum value that can be used) of the cache memory. It is necessary to install the maximum capacity required for the shared memory, or it is necessary to prompt the user to add the shared memory when the cache memory is added. For this reason, there has been a problem of placing a cost burden on the user.
[0019]
Therefore, as a solution, it can be considered that a part of the cache memory is used for storing control information of the disk array control apparatus to be stored in the shared memory. This is because the amount of additional shared memory is usually considerably smaller than the amount of additional cache memory.
[0020]
However, because the control information of the disk array controller to be stored in the shared memory is data that is short and frequently accessed, if part of it is placed in the cache memory and accessed, the influence of the protocol overhead As a result, there is a problem that the access performance is expected to deteriorate.
[0021]
The present invention has been made to solve the above-described problems of the prior art, and an object of the present invention is to respond to the addition of a cache memory unit in a disk control device having two types of memories, a cache memory unit and a shared memory unit. It is an object of the present invention to provide a disk control device that does not require an additional shared memory section and that does not deteriorate access performance.
[0022]
[Means for Solving the Problems]
A transfer path is provided between the cache memory unit and the shared memory unit. Then, the control data of the disk controller is transferred using the shared network of the shared memory unit as before, and the cache memory unit dedicated data is transferred through the transfer path between the newly provided cache memory unit and the shared memory unit. Transfer data to the buffer. The cache memory unit access right is arbitrated between the conventional cache access and the access via the transfer path between the cache memory unit and the shared memory unit, and writing to the memory is performed. This makes it possible to store some shared memory data in the cache memory without changing the protocol performance.
[0023]
In this way, since the access is made through the connection of the shared memory, even the data stored in the cache memory can be accessed without degrading the performance due to the overhead of the cache memory data protocol. Become. In addition, by devising the control of the memory controller, the data from the shared memory unit can be stored in the memory in the gap of the data write time from the cache memory data path to the memory, and the memory path efficiency is increased. Is possible.
[0024]
DETAILED DESCRIPTION OF THE INVENTION
Hereinafter, an embodiment according to the present invention will be described with reference to FIGS. 1, 3 to 13.
[0025]
[Combined network of shared memory and cache memory]
First, a combined network of shared memory and cache memory will be described with reference to FIGS.
FIG. 3 and FIG. 4 show another type of disk in which each IF unit is connected via a mutual connection network using a switch instead of the shared bus 16 shown in FIG. 2 as a connection network of the shared memory and the cache memory. It is a block diagram of an array control apparatus.
[0026]
Here, in the example shown in FIG. 3, both the shared memory and the cache memory connection network are connected networks using switches, and in the example shown in FIG. 4, only the cache memory connection network uses switches. It is a connected network.
[0027]
In the disk array control apparatus 2B of FIG. 3, the shared memory unit 13, the host IF unit 11, and the disk IF unit 12, and the cache memory unit 14, the host IF unit 11, and the disk IF unit 12 are not connected. , Respectively, are connected by an interconnection network 21 and an interconnection network 22 each composed of a crossbar switch.
[0028]
In this method, the throughput of each interconnected path is a fraction of the shared bus, but there are multiple paths between the two interconnected points, so the load is distributed and the throughput is improved. It becomes possible.
[0029]
Furthermore, a disk array control apparatus shown in FIG. 4 in which the combined network of the shared memory and the cache memory is another type can be considered.
[0030]
In this configuration, the cache memory unit 14, the host IF unit 11, and the disk IF unit 12 are connected to each other through the cross-connect switch 22 as in FIG. The IF unit 11 and the disk IF unit 12 are directly connected.
[0031]
As described above, in FIG. 4, the shared memory coupling network 21 and the cache memory coupling network 22 are distinguished from each other, and the independent configuration is attributed to the types of data handled by both. That is, the cache memory unit 14 is a memory that temporarily stores data read from the disk while it is being stored in the host. Therefore, there are many sequential accesses such as packet data transfer with a long data length. Is important.
[0032]
On the other hand, since the shared memory unit 13 is a memory for storing the control information of the apparatus, memory access with many random accesses increases, and there is a characteristic of emphasizing response. This is because the characteristics of these two accesses are contradictory, and if they are transferred by the same route and protocol, either performance will be reduced.
[0033]
In the apparatus of FIG. 4, unlike FIG. 3, the shared memory coupling network 21 of the shared memory unit 13 is a direct coupling that does not use the CSW (crossbar switch) unit, which is convenient for shortening the response time. Is good. On the other hand, the cache memory connection network 22 of the cache memory unit 14 has a large configuration, but has a structure in which the CSW (crossbar switch) unit is hierarchized in order to perform multiple accesses and increase the use band.
[0034]
[Configuration of disk controller]
Next, the configuration of the disk controller according to the present invention will be described with reference to FIG.
FIG. 1 is a configuration diagram of a disk control apparatus according to the present invention.
[0035]
The disk control device 1 of this embodiment includes a host IF unit 11 for having an interface with the host computer 50 and a disk IF unit 12 for having an interface with the magnetic disk device 20. Usually, a plurality of these interfaces are often provided in order to improve performance by parallel processing. In FIG. 1, two of each are shown. The disk control device 1 has two types of memories, a cache memory unit 14 and a shared memory unit 15, which are used for different purposes, and are connected to a host IF unit 11 and a disk IF unit 12, respectively. Hereinafter, the cache memory may be referred to as “CM” and the shared memory may be referred to as “SM”.
[0036]
The host IF unit 11 includes a host IF 3, a microprocessor 6, a CM access control unit 4a, and an SM access control unit 5a. The host IF 3 is a part in charge of the interface with the host computer 50. The microprocessor 6 is a part that controls input / output with respect to the host computer 50. The CM access control unit 4 a is a part that controls access to the cache memory unit 14. The SM access control unit 5 a is a part that controls access to the shared memory unit 15.
[0037]
The host IF unit 11 executes data transfer between the host computer 50 and the cache memory unit 14 under the control of the microprocessor 6. As shown in FIG. 1, the microprocessor 6 and the host IF 3 are connected by an internal bus, and the CM access control unit 4 is also connected to the host IF 3.
[0038]
Similarly, the SM access control unit 5a also transfers data using the SM path 40 connected to the shared memory unit 15 under the control of the microprocessor 6.
[0039]
The disk IF unit 12 includes a drive IF 2, a microprocessor 6, a CM access control unit 4b, and an SM access control unit. 5b have.
[0040]
The drive IF2 is a part in charge of the interface with the magnetic disk device 20. The microprocessor 6 is a part that controls input / output to the magnetic disk device 20. The CM access control unit 4 b is a part that controls access to the cache memory unit 14. The SM access control unit 5 b is a part that controls access to the shared memory unit 15.
[0041]
The disk IF unit 12 executes data transfer between the magnetic disk device 20 and the cache memory unit 14 under the control of the microprocessor 6. As shown in FIG. 1, the microprocessor 6 and the drive IF2 are connected by an internal bus, and the CM access control unit 4b is connected to the drive IF2. The disk IF unit also executes arithmetic functions such as RAID control.
[0042]
Similarly, the SM access control unit 5b Also, the data is transferred using the SM path 40 connected to the shared memory unit 15 under the control of the microprocessor 6.
[0043]
The cache memory unit 14 is a memory provided to improve access performance by temporarily storing and accessing data read / written from / to the magnetic disk device 20. A plurality of cache memory units 14 are installed according to demands on the capacity and performance of the magnetic disk 20 with the CM controller 7 and the memory module 9 as one unit.
[0044]
The host IF unit 11 and the disk IF unit 12 are connected to the crossbar switch unit 13 by the CM path 0 (31), and the cache memory unit 14 is connected by the CM path 1 (32).
[0045]
That is, the CM path 0 (31) is connected to the CM access control unit 4a of the host IF unit 11 and the CM access control unit 4b of the disk IF unit 12, and the CM controller unit 7 of the cache memory unit 14 Path 1 (32) is connected. Each CM path 0 (31) connected to the plurality of CM access control units 4a and 4b and each CM path 1 (32) connected to the plurality of CM controller units 7 are crossbar switch (CSW) units. 13 are connected hierarchically.
[0046]
The shared memory unit 15 is a memory that stores control data for the disk control device 1. In particular, the shared memory unit 15 stores management information necessary for exclusive control of access to the cache memory unit 7 as control data. A plurality of shared memory units 15 are also installed in response to a request for performance, with the SM controller 7 and the memory module 9 as one unit.
[0047]
The shared memory unit 15 is connected to the host IF unit 11 and the disk IF unit 12 by the SM path 40.
[0048]
That is, the SM access control unit 5 a of the host IF unit 11 and the SM access control unit 5 b of the disk IF unit 12 are connected to the SM controller unit 8 of the shared memory unit 15 via the SM path 40.
[0049]
Here, unlike the CM path, the hierarchical structure with the crossbar switch is different from the cache memory data in that the shared memory data is small in capacity, has many transactional accesses, and has a short response time. Since it is indispensable, it also has the effect of reducing the protocol overhead time due to switching. That is, the meaning of having a path in which the cache memory unit and the shared memory unit are separated is because the nature of data access is different.
[0050]
Further, the SM controller 8 of the shared memory unit 15 and the CM controller 8 of the cache memory unit 14 are connected by a unique CM / SM transfer path 41, and control data stored in the shared memory unit 15 in the past is stored. Can also be stored in the cache memory unit 14 via the CM / SM transfer path 41.
[0051]
This connection form may be a form in which the shared memory unit 15 and the cache memory unit 14 are connected in a one-to-one relationship, or a one-to-many connection in which a plurality of cache memory units 14 are connected to one shared memory unit 15. It may be connected.
[0052]
[Detailed configuration of each part of each disk controller]
Next, a more detailed configuration of each part of the disk controller according to the present invention will be described with reference to FIGS.
(I) CM access control unit
First, the configuration of the CM access control units 4a and 4b will be described with reference to FIG.
FIG. 5 is a configuration diagram of the CM access control units 4a and 4b.
[0053]
The CM access control unit 4 includes a selector 102, a packet buffer 103 for temporarily storing addresses, commands, and data, a path IF 101 for CM path 0 (31) connected to the crossbar switch unit 13, and a data error check. The circuit unit 100 and the data transfer control unit 110 are included.
[0054]
The two ports of the selector 102 are connected to the host IF 3 or the drive IF 2 by the data line 29.
[0055]
The other two ports of the selector 102 are connected to the path IF 101 via the packet buffer 103, and the path IF 101 is connected to the crossbar switch unit 13 via the CM path 0 (31). The data transfer control unit 110 is connected to the data transfer control unit 132 in the crossbar switch unit 13 (shown later in FIG. 7) by a control line 2 (33). The data transfer control unit 110 arbitrates an access request from the host IF 3 or the drive IF 2 by the arbiter 108 and switches to the selector 102.
(II) SM access control unit
Next, the configuration of the SM access control units 5a and 5b will be described with reference to FIG. FIG. 6 is a configuration diagram of the SM access control units 5a and 5b.
[0056]
The SM access control unit 4 includes a selector 112, a packet buffer 113 for temporarily storing addresses, commands, and data, a path IF 111 for SM path 0 (31) connected to the crossbar switch unit 13, and a data error check. The circuit unit 114 and the data transfer control unit 115 are included.
[0057]
The two ports of the selector 102 are connected to the host IF 3 or the drive IF 2 by the data line 28.
[0058]
The other two ports of the selector 102 are connected to the path IF 101 via the packet buffer 113, and the path IF 101 is directly connected to the shared memory unit 15 via the SM path 40. The data transfer control unit 115 is connected to the data transfer control unit 152 in the shared memory unit 15 (shown later in FIG. 9) by the control line 2 (36). The data transfer control unit 115 arbitrates an access request from the host IF 3 or the drive IF 2 by the arbiter 118 and switches to the selector 112.
(III) Crossbar switch section
Next, the configuration in the crossbar switch unit 13 will be described with reference to FIG. FIG. 7 is a configuration diagram of the crossbar switch unit 13.
[0059]
The crossbar switch (CSW) unit 13 includes a selector 136 that connects the CM path 0 (31) and the CM path 1 (32) to each other, a packet buffer 133, a path IF 131, and a data error check circuit unit. 130, an address / command analysis unit 135 that analyzes an address and a command transmitted from the CM access control unit 4, and a data transfer control unit 132.
[0060]
The CM path 0 (31) is connected to the host IF unit 11 and the disk IF unit 12, and the CM path 1 (32) is connected to the CM controller 7 in the cache memory unit 14.
[0061]
The data transfer control unit 132 is connected to the data transfer unit 110 in the CM access control unit 4 shown in FIG. 5 by the control line 2 (33), and in the cache memory unit 14 by the control line 3 (34). It is connected to a data transfer control unit 148 (shown in FIG. 7) in the CM controller 7. Further, the data transfer control unit 132 performs arbitration of the access request from the CM path 0 (31) analyzed by the address / command analysis unit 135 by the arbiter 138, and switches the selector 136.
[0062]
When there is a difference in data transfer speed between the path on the CM path 0 (31) side and the path on the CM path 1 (32) side, the packet buffer 133 partially or entirely transfers data to absorb the speed difference. Is buffered.
[0063]
The address / command analysis unit 135 includes a buffer for storing addresses and commands, an address extraction unit, and a command extraction unit (not shown). The address / command analysis unit 135 stores addresses and commands in a plurality of CM paths 0 (31) connected to the CM access control unit 4 and buffers allocated to the respective CM paths 0 (31). The address extraction unit and command extraction unit determine the CM controller 7 to be accessed and send it to the arbiter 138 in the data transfer control unit 132.
(IV) Cache memory section
Next, the configuration in the cache memory unit 14 will be described with reference to FIG.
FIG. 8 is a configuration diagram of the cache memory unit 14.
[0064]
The cache memory unit 14 includes a CM controller 7 and a memory module 9.
[0065]
The CM controller 7 includes a path IF 141, a selector 144, a packet buffer 143 that temporarily stores data, a data error check circuit unit 140, a memory control unit 147 that controls access to the memory module 9, and CM access An address / command analysis unit 145 that analyzes an address and a command transmitted from the control unit 4 and a data transfer control unit 148 are included.
[0066]
The CM controller 7 is connected to the crossbar switch unit 13 by CM path 1 (32).
The data transfer control unit 148 sends an access request from the CM path 1 (32) analyzed by the address / command analysis unit 145 by the arbiter 180 and the SM controller 8 (shown in FIG. 9 later) that is a feature of the present invention. Arbitration with the access request is performed from the SM / CM path 41 to be connected, and the selector 144 is switched.
[0067]
The address / command analysis unit 145 includes a buffer, an address extraction unit, and a command extraction unit (not shown). The address / command analysis unit 145 stores an address and a command in a buffer assigned to each CM path 1 (32) connected to the CM controller 7. The address extraction unit and command extraction unit determine the address of the memory to be accessed and the type of access, and send them to the memory control unit 147. Further, an access request from the CM path 1 (32) is sent to the arbiter 148 in the data transfer control unit 148.
(V) Shared memory section
Next, the configuration in the shared memory unit 15 will be described with reference to FIG.
FIG. 9 is a configuration diagram of the shared memory unit 15.
[0068]
The shared memory unit 15 includes an SM controller 8 and a memory module 9.
[0069]
The SM controller 8 includes a path IF 151, a selector 156, a packet buffer 153 for temporarily storing data, a data error check circuit unit 150, a memory control unit 157 for controlling access to the memory module 9, and an SM access. An address / command analysis unit 155 that analyzes an address and a command transmitted from the control unit 4 and a data transfer control unit 152 are included.
[0070]
The SM controller 8 is directly connected to the SM access control units 5a and 5b through the SM path 40.
The data transfer control unit 152 uses the arbiter 158 to arbitrate the access request from the SM path 40 analyzed by the address / command analysis unit 155, and switches the selector 154, that is, as shown in FIG. It is selected whether to connect to the module 9 or to connect to the SM / CM path 41 connected to the CM controller 7 shown in FIG. 8 via the path IF 151.
[0071]
The address / command analysis unit 155 includes a buffer, an address extraction unit, and a command extraction unit (not shown). The address / command analysis unit 155 stores an address and a command in a buffer assigned to each SM path 40 connected to the SM controller 7. The address extraction unit and command extraction unit determine the address of the memory to be accessed and the type of access, and send them to the memory control unit 157. Further, an access request from the SM path 40 is sent to the arbiter 158 in the data transfer control unit 152.
[0072]
[Memory access operation]
Next, the memory access operation of the disk controller according to the present invention will be described in detail with reference to FIGS.
(I) Access to cache memory
First, an access procedure of the cache memory unit 14 will be described.
When accessing the cache memory unit 14, the microprocessor 6 instructs the host IF 3 or the drive IF 2 to start access to the cache memory unit 14.
[0073]
The host IF 3 or drive IF 2 receiving the access start instruction sends a signal indicating the access start to the data transfer control unit 110 in the CM access control units 4a and 4b shown in FIG. 5 through the control line 1 (30). At the same time, an address, command, and data are transmitted through the data line 29.
[0074]
The CM access control unit 4 stores the address, command, and data sent through the data line 29 in the packet buffer 103. The data transfer control unit 110 performs arbitration, determines the right to use the path IF 101, and switches the selector 102.
(I-1) Cache write access
Here, a procedure for writing data to the cache memory unit 14 will be described with reference to FIG.
FIG. 10 is a sequence diagram illustrating a flow of access from the CM access control units 4a and 4b to the CM controller 7 when data is written to the cache memory unit 14.
[0075]
When the right to use the CM path 0 (31) is determined by arbitration, the data transfer unit 110 in the CM access control units 4a and 4b shown in FIG. 5 is controlled by the control line 2 (33) by the crossbar switch unit. A signal (REQ) indicating the start of access is output to the data transfer control unit 1 (32) in 13 (sequence 501). Subsequently, an address and a command are transmitted (sequence 502).
[0076]
The data transfer control unit 132 in the crossbar switch unit 13 shown in FIG. 7 receives the REQ signal from the CM access control unit 4 and then receives the address and command sent through the CM path 0 (31). Then, arbitration is performed based on the access request analyzed by the address / command analysis unit 135 (sequence 503). If the right to connect to the CM path 1 (32) is obtained as a result of the arbitration, the data transfer control unit 132 switches the selector 136 (sequence 504). Then, the control line 2 (33) returns a signal (ACK) indicating that the connection to the CM path 1 (32) is obtained to the data transfer control unit 110 in the CM access control units 4a and 4b (sequence 505). ).
[0077]
Next, the data transfer control unit 132 in the crossbar switch unit 13 receives a signal (REQ) indicating the start of access to the data transfer control unit 148 in the CM controller 7 shown in FIG. 8 through the control line 3 (32). ) Is issued (sequence 506). Subsequently, an address and a command are transmitted (sequence 507).
[0078]
When receiving the ACK signal, the CM access control units 4a and 4b read the data from the packet buffer 103 and send it to the CM path 0 (31) via the selector 102 and the path IF 101. The crossbar switch unit 13 sends the data sent through the CM path 0 (31) to the CM path 1 (32) via the path IF 131 and the selector 136 (sequence 509).
[0079]
When the data transfer control unit 148 in the CM controller 7 receives the REQ signal through the control line 3 (34), it next receives the address and command sent through the CM path 1 (32), and performs address / command analysis. Arbitration is performed based on the access request analyzed by the unit 145 (sequence 508), and the selector 144 is switched. Data sent through the CM path 1 (32) is stored in the packet buffer 143.
[0080]
When the access right to the memory module 9 is obtained as a result of the arbitration, the memory control information is sent to the memory control unit 147 and preprocessing for memory access is performed (sequence 510). Next, data is read from the packet buffer 143 and written to the memory module 9 via the selector 304 (sequence 511).
[0081]
When the access to the memory module 9 is completed, the CM controller 7 performs post-processing of memory access and generates status information (STATUS) indicating an access result (access status) in the data transfer control unit 148 (sequence 512). Next, status information is sent to the CM access unit 4 via the crossbar switch unit 13 (sequence 513). When receiving the status information (STATUS), the data transfer control unit 148 in the crossbar switch unit 13 turns off the REQ signal to the CM controller 107 (sequence 514).
[0082]
Then, the data transfer control unit 110 in the CM access control unit 4 turns off the REQ signal to the crossbar switch unit 13 that receives STATUS (sequence 515). When confirming that the REQ signal from the CM access control unit 4 is turned off, the data transfer control unit 132 in the crossbar switch unit 13 turns off the ACK signal to the CM access control unit 4 (sequence 516). When the data transfer control unit 110 in the CM access control unit 4 receives the status, it reports the end of access to the cache memory unit 14 to the host IF 11 or the drive IF 12 through the control line 1 (30).
(I-2) Cache read access
Next, a procedure for reading data from the cache memory unit 14 will be described.
[0083]
When data is read from the cache memory unit 14 (read operation), the flow of access from the CM access control unit 4 to the CM controller 7 is the same as that in sequences 501 to 508, and in the sequence 512 and later, data is written (write). Operation). Here, when receiving the ACK signal in sequence 506, the CM access control unit 4 enters a data reception waiting state.
[0084]
When obtaining the memory access right in the sequence 508, the CM controller 7 reads data from the memory module 9 and sends the data to the CM path 1 (32) via the selector 144 and the path IF 141. When the crossbar switch unit 13 receives the data through the CM path 1 (32), the crossbar switch unit 13 outputs the data to the CM path 0 (31). The CM access control units 4a and 4b receive the host IF3 via the selector 102 and the data line 29. Alternatively, data is transmitted to the drive IF2.
(II) Access to shared memory
Next, an access procedure of the shared memory unit 15 will be described.
[0085]
When accessing the shared memory unit 15, the microprocessor 6 instructs the host IF 3 or the drive IF 2 to start access to the shared memory unit 15.
[0086]
The host IF 3 or the drive IF 2 receiving the access start instruction sends a signal indicating access start to the data transfer control unit 115 in the SM access control units 5a and 5b shown in FIG. 6 through the control line 1 (35). At the same time, the address, command, and data are transmitted through the data line 28.
[0087]
The SM access control units 5 a and 5 b store the address, command, and data sent through the data line 28 in the packet buffer 113. The data transfer control unit 115 performs arbitration, determines the right to use the path IF 111, and switches the selector 112.
(II-1) Shared memory write access
First, the procedure for writing data to the shared memory unit 15 will be described with reference to FIG.
FIG. 11 is a sequence diagram showing a flow of access from the SM access control units 5a and 5b to the SM controller 8 when data is written to the shared memory unit 15.
[0088]
When the right of use of the SM path 40 is determined by arbitration, the data transfer unit 115 in the SM access control units 5a and 5b shown in FIG. 6 is controlled by the control line 2 (36) in the SM access control units 5a and 5b. A signal (REQ) indicating the start of access is output to the data transfer control unit 115 (sequence 601). Subsequently, an address and a command are transmitted (sequence 602). The data transfer control unit 152 in the SM controller 8 of the shared memory unit 15 shown in FIG. 9 receives the REQ signal from the SM access control units 5a and 5b, and then receives the address and command sent through the SM path 40. Arbitration is performed based on the access request received and analyzed by the address / command analysis unit 155 (sequence 603). As a result of arbitration, when the connection right is obtained, the data transfer control unit 152 switches the selector 156 (sequence 504).
[0089]
When the data transfer control unit 152 in the SM controller 8 receives the REQ signal through the control line 2 (35), the data transfer control unit 152 receives the next address and command sent through the SM path 140 and analyzes them by the address / command analysis unit 155. Based on the received access request, arbitration is performed (sequence 608), and the selector 156 is switched. Data sent through the SM path 40 is stored in the packet buffer 153.
[0090]
As a result of the arbitration, when the access right to the memory module 9 is obtained, the data transfer control unit 152 sends the memory control information to the memory control unit 157 and performs preprocessing for memory access (sequence 610). . Next, data is read from the packet buffer 153 and written to the memory module 9 via the selector 156 (sequence 611).
[0091]
When the access to the memory module 9 is completed, the SM controller 8 performs post-processing of memory access, and the data transfer control unit 152 generates status information (STATUS) indicating the access result (access status) (sequence 612). Next, status information is sent to the SM access control units 5a and 5b (sequence 613). When receiving the status information (STATUS), the data transfer control unit 115 in the SM access control units 5a and 5b turns off the REQ signal to the SM controller 8 (sequence 614). The end of access to the shared memory unit 15 is reported to the host IF 3 or the drive IF 2 through the control line 1 (35).
(II-2) Shared memory read access
Next, a procedure for reading data from the shared memory unit 15 will be described.
[0092]
When reading data from the shared memory unit 15 (read operation), the flow of access from the SM access control units 5a and 5b to the SM controller 8 is the same as that from sequence 601 to sequence 608. This is the same as the case (write operation).
[0093]
When the memory access right is obtained in the sequence 608, the SM controller 8 reads data from the memory module 9 and sends the data to the SM path 40 via the selector 156 and the path IF 151. The SM access control units 5a and 5b send data to the host IF 3 or the drive IF 2 via the selector 112 and the data line 28.
(III) SM data / CM access
As described above, the feature of the present invention is that the SM / CM path 41 is provided between the cache memory unit 14 and the shared memory unit 15, and control data stored in the shared memory unit 15 in the past is transferred to this path. In other words, the data can be stored in the cache memory unit 14.
[0094]
As a condition for performing such transfer, when data to be stored in the cache memory unit is determined in advance (for example, management information from a certain address in the cache memory is determined to be stored in the cache memory). There are two cases where data cannot be stored in the shared memory unit 15.
[0095]
Hereinafter, a procedure for transferring data from the SM control unit to the CM control unit through the SM / CM path 41 will be described with reference to FIGS. 12 and 13.
FIG. 12 is a sequence diagram showing a procedure for transferring data from the SM control unit to the CM control unit using the SM / CM path 41.
FIG. 13 is a flowchart showing an outline of the operation of the CM controller 7 of the cache memory unit 14.
[0096]
The flow of access from the SM access control units 5a and 5b to the SM controller 8 of the shared memory unit 15 when data is transferred from the shared memory unit 15 to the cache memory (write operation) is the sequence 601 shown in FIG. To sequence 604.
[0097]
In sequence 602, the SM controller 8 receives the address / command, and further stores data sent through the SM / CM path 1 (41) in the SM buffer 143 (sequence 704). When the SM controller 8 receives all the data and completes transmission of the data to the CM controller 9 through the SM / CM path, the data transfer control unit 152 displays status information (STATUS) indicating an access result (access status). Generate (sequence 605). Next, status information is sent to the SM access control units 5a and 5b (sequence 613).
[0098]
In this case, note that the SM controller 8 can proceed without waiting for a response from the CM controller 7.
[0099]
When the data transfer control unit 115 in the SM access control units 5a and 5b receives the status information (STATUS), it turns off the REQ signal to the SM controller 8 (sequence 614). Then, the control line 1 (35) reports the end of access to the shared memory unit 15 to the host IF 3 or the drive IF 2.
[0100]
On the other hand, after receiving data in sequence 704, the CM controller 9 performs arbitration based on the access request analyzed by the data address / command analysis unit 155 (sequence 705), and obtains the right to access the memory module 9. Sometimes, the selector 156 is switched to the connection to the SM / CM 41 (sequence 706). Then, the CM controller 9 sends memory control information to the memory control unit 147, performs preprocessing for memory access, reads data from the packet buffer 143, and writes the data to the memory module 9 via the selector 304 (sequence 707). ), The access to the memory module 9 is terminated.
[0101]
An outline of the operation of the CM controller 7 of the cache memory unit 14 during this period is as shown in FIG.
[0102]
The address / command analysis unit 145 of the CM controller 7 analyzes whether REQ is ON (S801, S802).
[0103]
When REQ is ON, arbitration is performed by the arbiter 180 of the data transfer control unit 148 (S805).
[0104]
When the REQ signal is not ON, it is checked whether data has arrived in the SM buffer 149 connected to the SM / CM path 41. When the data has arrived, command analysis is performed by the address / command analysis unit 145, and the data Arbitration is performed by the arbiter 180 of the transfer control unit 148 (S805).
[0105]
As a result, when the output port of the CM path can be acquired (S806), the selector is switched and the CM path 1 (32) and the memory module 9 are connected according to the result of the address / command analysis (S807). Then, data is written to or read from the memory module 9 (S808).
[0106]
Next, STATUS information is received or transmitted (S809), and finally REQOFF is received and terminated (S810).
[0107]
If the SM path output port can be acquired (S811), the selector is switched, and the SM / CM path 41 and the memory module 9 are connected according to the result of the address / command analysis (S812). Then, data is written to or read from the memory module 9 (S813).
[0108]
If neither output port can be acquired, arbitration is repeated until an output port can be acquired.
[0109]
【The invention's effect】
According to the present invention, in a disk control device having two types of memories, a cache memory unit and a shared memory unit, it is not necessary to add a shared memory unit according to the addition of the cache memory unit, and the access performance is reduced. It is possible to provide a disk control device that does not.
[Brief description of the drawings]
FIG. 1 is a configuration diagram of a disk control device according to the present invention.
FIG. 2 is a configuration diagram of a disk array control device in which the internal configuration according to the prior art is a shared bus connection.
FIG. 3 is a configuration diagram of a disk array control apparatus that connects IF units via a mutual coupling network using switches as a coupling network of a shared memory and a cache memory.
FIG. 4 is a configuration diagram of a disk array control apparatus that connects IF units via a mutual connection network using a switch only to the cache memory connection network as a connection network of the shared memory and the cache memory.
FIG. 5 is a configuration diagram of CM access control units 4a and 4b.
FIG. 6 is a configuration diagram of SM access control units 5a and 5b.
7 is a configuration diagram of a crossbar switch unit 13. FIG.
FIG. 8 is a configuration diagram of a cache memory unit 14;
9 is a configuration diagram of the shared memory unit 15. FIG.
FIG. 10 is a sequence diagram showing a flow of access from the CM access control units 4a and 4b to the CM controller 7 when data is written to the cache memory unit 14;
11 is a sequence diagram showing a flow of access from the SM access control units 5a and 5b to the SM controller 8 when data is written to the shared memory unit 15. FIG.
FIG. 12 is a sequence diagram showing a procedure for transferring data from the SM control unit to the CM control unit using the SM / CM path 41;
FIG. 13 is a flowchart showing an outline of the operation of the CM controller 7 of the cache memory unit 14;
[Explanation of symbols]
DESCRIPTION OF SYMBOLS 1 ... Disk control apparatus, 2 ... Drive IF, 3 ... Host IF, 4 ... CM (cache memory) control part, 5 ... SM (shared memory) access control part, 6 ... Microprocessor part, 11 ... Host IF part, 12 ... disk IF unit, 13 ... CSW (crossbar switch) unit, 14 ... cache memory unit, 15 ... shared memory unit, 20 ... magnetic disk unit, 31 ... CM (cache memory) path 0, 32 ... CM (cache memory) Path 1, 40... SM (shared memory memory) path, 41 CM / SM path, 50 host computers.

Claims (6)

In a disk control device for accessing a magnetic disk device by a host computer,
A host interface unit having an interface with the host computer;
A disk interface unit having an interface with the magnetic disk device;
A cache memory unit for temporarily storing data to be read from and written to the magnetic disk device;
A shared memory unit for storing control data of the disk controller,
The cache memory unit stores the control data in addition to the data read / written to the magnetic disk device,
A path for data transfer is provided between the cache memory unit and the shared memory unit,
The disk control apparatus, wherein the control data is stored in the cache memory unit via the shared memory unit. The coupling of the cache memory unit, the host interface unit and the disk interface unit is a switch coupling,
2. The disk controller according to claim 1, wherein the shared memory unit, the host interface unit, and the disk interface unit are directly coupled.   2. The disk control apparatus according to claim 1, wherein the connection between the shared memory unit and the cache memory unit through the data transfer path is a one-to-one connection.   2. The disk controller according to claim 1, wherein the connection between the shared memory unit and the cache memory unit through the data transfer path is a one-to-many connection. In a data access method of a disk control device for accessing a magnetic disk device by a host computer,
This disk controller
A host interface unit having an interface with the host computer;
A disk interface unit having an interface with the magnetic disk device;
A cache memory unit for temporarily storing data to be read from and written to the magnetic disk device;
A shared memory unit for storing control data of the disk controller,
The cache memory unit stores the control data in addition to the data read / written to the magnetic disk device,
Furthermore, in this disk controller, a data transfer path is provided between the cache memory unit and the shared memory unit,
A data access method for a disk control device for storing control data for the disk control device in the cache memory unit via the shared memory unit. In a disk control device for accessing a magnetic disk device by a host computer,
A host interface unit having an interface with the host computer;
A disk interface unit having an interface with the magnetic disk device;
A cache memory unit for temporarily storing data to be read from and written to the magnetic disk device;
A shared memory unit for storing control data of the disk controller,
The cache memory unit stores the control data in addition to the data read / written to the magnetic disk device,
The host interface unit includes a host interface that interfaces with the host computer, a microprocessor that controls data transfer, a cache memory access control unit that controls access to the cache memory unit, and the shared memory unit. And a shared memory access control unit that performs access control of
The disk interface unit includes a drive interface that handles an interface with the magnetic disk device, a microprocessor that controls data transfer, a cache memory access control unit that controls access to the cache memory unit, and the shared memory unit And a shared memory access control unit that performs access control with
Each cache memory access control unit of the host interface unit and the disk interface unit is coupled to the cache memory unit via a crossbar switch,
The shared memory access control unit of each of the host interface unit and the disk interface unit is directly coupled to the shared memory unit,
The cache memory unit includes a cache memory controller and a memory module,
The shared memory unit includes a shared memory controller and a memory module,
The cache memory controller and the shared memory controller are coupled by a cache memory / shared memory path,
The disk controller according to claim 1, wherein the cache memory controller and the shared memory controller transfer the control data through the cache memory / shared memory path and store the data in a memory module of the cache memory unit.

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