JPH11175260A - Disk array controller and controlling method therefor - Google Patents

Abstract

PROBLEM TO BE SOLVED: To improve the throughput of a data transferring path by connecting an interface part with a host computer, an interface part with plural magnetic disk device and plural shared memory part to each other through the use of a switch. SOLUTION: Within a channel I/F part 11, two micro processors for control 100, two data transmission and reception control parts with a host computer (host I/F) 110 and a communication control part 111 between an inter face part - a shared memory part are connected through a shared bus 101. On the other hand, within a disk I/F part 12, two micro processors for control 105, data transmission and reception control parts 112 with plural magnetic disk devices 21 and a communication control part 111 between an inter face part and a shared memory part are connected through a shared bus 102. Then the parts 11 and 12 and plural shared memory parts 30 and 31 using a switch are connected by a mutual connecting network 50.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a control device for a disk array device which divides data and stores the data in a plurality of magnetic disk devices.

[0002]

2. Description of the Related Art The I / O performance of a subsystem using a magnetic disk device used as a secondary storage device is about three to four orders of magnitude smaller than the I / O performance of a main memory of a computer. Efforts are being made in various places to reduce the I / O performance of subsystems.
As one method for improving the I / O performance of a subsystem, a system in which a subsystem is composed of a plurality of magnetic disk devices and data is divided and stored in the plurality of magnetic disk devices, that is, a system called a so-called disk array It has been known. In this disk array, a plurality of magnetic disk devices are operated in parallel to input and output data, so that I / O performance is improved. However, since the writing and reading operations for a plurality of magnetic disk devices are processed in parallel, there is a problem that the control is complicated and the overhead required therefor is large.

As shown in FIG. 2, a controller 3 for a large disk array mainly for a mainframe generally includes an interface unit (channel I / F unit) 13 with the host computer 1 and a plurality of magnetic disk units. An interface unit (disk I / F unit) 14 and a shared memory unit 32 for temporarily storing data and control information are connected via a shared bus 60.

[0004] The I / O throughput performance of the disk array device has been greatly increased, and in order to cope with the increase, it is necessary to improve the processing performance of the interface unit and the like. With these improvements in processing performance, the utilization rate of the shared bus 60 has become saturated, which limits throughput performance. Therefore, although efforts have been made to increase the throughput of the shared bus 60, it is difficult to improve the bus width, the driving frequency, and the like due to the configuration of the device, and there is a limit in improving the throughput.

[0005]

The problems to be solved by the present invention are: an interface with a host computer (channel I / F); an interface with a plurality of magnetic disk devices (disk I / F); An object of the present invention is to improve the throughput of a data transfer path connected to a shared memory unit for temporarily storing data and control information.

[0006]

In order to solve the above-mentioned problems, in the present invention, the above-mentioned interface section and the like are connected to each other via an interconnection network using switches instead of the shared bus 60. As a result, the throughput of each interconnected path is a fraction of the number of shared buses, but since there are a plurality of paths between two interconnected points, the load is distributed and the throughput is improved. Becomes possible.

[0007] In fact, the present inventor has proposed a switch (SW).
A disk array control device using an interconnection network according to
As a result of comparing the disk array control device 3 in which the channel I / F unit 13, the disk I / F unit 14, and the shared memory unit 32 are connected by the shared bus 60 shown in FIG. 2, FIG.
FIG. 5 is a diagram of a response curve with the / O throughput and the vertical axis representing the access time to the shared memory. The horizontal axis represents the limit I / O throughput of the disk array controller using the interconnection network as 1
The vertical axis indicates the relative value when the shared memory access time of the disk array controller using the shared bus at a low load is set to 1. As shown in (1), it has been clarified that the disk array controller using the interconnection network has a higher limit I / O throughput.

On the other hand, regarding the access time to the shared memory, when the I / O throughput is low (low load),
It has also been found that the disk array controller 3 using the shared bus system shown in FIG. 2 is shorter. this is,
Interconnection network, channel I / F section, disk I / F section,
(SWI / SWI /
This is due to the processing latency in F) and in the SW forming the interconnection network. In order to reduce the processing latency, it is necessary to occupy all the via switches from the channel I / F or the disk I / F to the shared memory before accessing the shared memory. However, when such an access method is adopted, the limit I / O throughput becomes low.

Therefore, in another invention of the present application, at least one interface unit with a host computer, one interface unit with a plurality of magnetic disk devices, and a plurality of physically independent units for storing data and control information. A disk array control, wherein the interface unit with the host computer, the interface unit with the plurality of magnetic disk devices, and the plurality of shared memory units are connected by an interconnection network using SW. An interface unit with the host computer, an interface unit with the plurality of magnetic disk devices, an interface unit with an interconnection network, a unit for measuring an access time to the shared memory unit, Means for calculating an average value of access time; Means for selecting an access method to the shared memory unit based on the average value between the two, and storing the method in transmission data, and in the SW forming the interconnection network, based on the transmission data. In the disk array control device having means for occupying the selected path until the shared memory access by the data is completed, at the time of system startup, a shared memory access method that shortens the access time is set, If the average access time to the shared memory unit exceeds a predetermined value, the method switches to a shared memory access method capable of increasing the I / O throughput. Based on the magnitude relation between the set values, control is performed to switch between the two access methods.

As an example of the above two access methods,
The following methods are conceivable. As a method of shortening the access time to the shared memory unit, a method of establishing an entire path to the shared memory unit before data transfer and occupying the path until the shared memory access is completed (connection type access method) is considered. Can be On the other hand, as a method capable of increasing the I / O throughput, the entire path to the shared memory unit is not established before the data transfer, and
A method of establishing a path to W and releasing the path when the transfer to the SW is completed (connectionless access method) can be considered. .

At the time of low I / O throughput (low load), the former method has a shorter access time to the shared memory section than the latter method. However, in the former method, the access time to the shared memory unit is rapidly increased at a lower I / O throughput than the latter method. That is,
Limit I / O throughput is reduced. Therefore,
As shown in the present invention, high I / O is achieved by switching between two shared memory access schemes having contradictory characteristics based on the access time to the shared memory unit.
The access time when the I / O throughput is low (low load) can be reduced without impairing the throughput.

In actual control, a connection-type access method is selected in an initial state.

In the case where access to the shared memory is performed by a connection-type access method, an interface with an interconnecting network in the interface with the host computer or the interface with the plurality of magnetic disk devices is provided. The unit switches to the connectionless access method when the calculated average value of the access time to the shared memory unit becomes larger than a preset value.

When access to the shared memory unit is performed by a connectionless access method, an interface unit with the host computer;
Alternatively, in the interface unit with the interconnection network of the interface unit with the plurality of magnetic disk devices,
When the calculated average value of the access time to the shared memory unit is smaller than a preset value, the connection is switched to the connection-type access method. This allows
It is possible to provide a disk array control device having a high I / O throughput limit and a short response time of the entire system and a control method thereof.

In the above-described disk array control device, the method of accessing the shared memory is stored in the data transmitted from the interface with the interconnection network to the shared memory unit, and transmitted to the SW in the interconnection network. By providing a path for direct transmission to all the via switches from the interface unit with the interconnection network to the shared memory unit, it is possible to reduce the time required for transmission,
The shared memory access time can be reduced.

[0016]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in detail below.

(Embodiment 1) FIG. 1 shows an embodiment of the present invention.

An interface unit (channel I / F) with the host computer 1 in the disk array controller 2
Unit) 11, an interface unit (disk I / F unit) 12 with a plurality of magnetic disk devices 21, and two shared memory units 30, 31 via an interconnection network 50 using switches (SW). Have been.

The interconnection network 50 using SWs includes at least one SW having a plurality of ports. The port of each SW is connected to another SW or each interface unit and the shared memory unit in the disk array control device. In the present embodiment, four SWs 40 each having five ports for input and output are interconnected as shown in FIG. 8 (interconnection network 50) which are mutually connected (topology called a complete connection network), or as shown in FIG. An interconnection network 51 including one SW 41 having eight ports for input and output is used. In the figure, the input / output ports are collectively shown as one line. There is no problem in implementing the present embodiment even if an interconnection network having another topology is used.

In the channel I / F section 11, two control microprocessors 100, two data transmission / reception control sections (host I / F) 110 with the host computer, and a communication control section between the interface section and the shared memory section (SW I / F) 111 is connected via the shared bus 101. In the disk I / F unit 12, two control microprocessors 105, a data transmission / reception control unit (drive I / F) 11 with a plurality of magnetic disk devices 21.
2, and a communication control unit (SW I / F) 111 between the interface unit and the shared memory unit is connected via the shared bus 102. In the shared memory units 30 and 31, a communication control unit (SW) between the interface unit and the shared memory unit
The memory control unit 36 and the memory module 35 are connected via an I / F 113.

A data read request from the host computer 1 to the disk array controller 2 is sent to the host I / F
The signal is transmitted to the microprocessor 100 through 110.
The microprocessor 100 checks whether the requested data exists in the shared memories 30 and 31 or not.
Communication is performed through the I / Fs 111 and 113. If the requested data exists, the microprocessor 100 executes a reading process from the shared memory unit. If the request data does not exist, the microprocessor 100 issues an instruction to transfer the request data from the magnetic disk device 21 to the shared memory unit 30 or 31, and sends the command to the shared memory unit 30 or 31.
To one of the microprocessors 105 in the disk I / F unit 12 via This communication is also SW I /
This is performed through F111 and F113. The microprocessor 105 that has received the command reads the requested data from the magnetic disk device 21 through the drive I / F 112, and
The data is transferred to the shared memory unit 30 or 31 through the I / Fs 111 and 113. When the transfer is completed, the microprocessor 105 notifies the microprocessor 100 of a transfer end report via the shared memory unit 30 or 31. In response, the microprocessor 100 executes a process of reading request data from the shared memory unit 30 or 31 to the host computer 1. These communications are also performed through the SW I / Fs 111 and 113.

A data write request from the host computer 1 to the disk array controller 2 is sent to the host I / F
The signal is transmitted to the microprocessor 100 through 110.
The microprocessor 100 executes a writing process to the shared memory unit 30 or 31. In addition, the fact that the data has been written to the shared memory is notified to one of the two microprocessors 105 via the shared memory unit 30 or 31.
Tell one. These communications are also performed by the SW I / F 111, 1
13 through. Microprocessor 1 notified
05 is the disk I from the shared memory unit 30 or 31
The data is transferred to the / F unit 12 through the SW I / Fs 111 and 113, and is written to the magnetic disk device 21 through the drive I / F 112.

FIG. 4 is a diagram showing the SW in the channel I / F unit 11.
The configuration of the I / F 111 is shown. FIG. 7 shows the SW
4 shows a flow of selecting a shared memory access method in the communication controller 140 in the I / F 111.
The communication between the channel I / F unit 11 and the shared memory units 30 and 31 will be described with reference to FIGS. Channel I /
In the F section 11, two control microprocessors 10
0, a host I / F 110 and a SW I / F 111 are connected via a shared bus 101.

First, control information transmitted from the microprocessor 100 or data from the host I / F 110 (hereinafter, the two are collectively referred to as transmission data) are first transmitted.
This is sent to the communication controller 140. Therefore, the transmission data is stored in the buffer 135. The communication controller 140 selects a shared memory access method and stores the information in the header of the transmission packet. The packet generation unit 120 generates a packet by combining the header with the transmission data stored in the buffer 135, and sends the packet to the interconnection network 50. When the packet is transmitted, the communication controller 1
The timer 130 in 40 is started, and measurement of the time required for accessing the shared memory units 30 and 31 is started.

When the packet is returned from the shared memory unit, the timer 130 is stopped, the communication control controller records the shared memory access time, and calculates the average access time from the previous access time. The transmitted packet is sent to the packet
Decompose the data into a header and transmission data
35. Thereafter, the communication control controller 140
To the microprocessor 100 or the host I / F 110.

Next, a method of selecting a shared memory access method in the communication controller will be described with reference to FIG.

In this embodiment, one of the following two access methods is selected to access the shared memory units 30 and 31. One is a method in which the access time to the shared memory units 30 and 31 is shortened. A method in which the entire path to the shared memory units 30 and 31 is established before data transfer and occupied until the shared memory access is completed ( Connection-type access method). The other is a method that can increase the I / O throughput, and does not establish the entire path to the shared memory units 30 and 31 before data transfer, but establishes a path to the next transit SW. This is a method of releasing the path when the transfer to the SW is completed (connectionless access method).

In the initial state, a connection type access method is selected (201). Next, the process waits 202 until a shared memory access occurs 202. When a shared memory access occurs, first, the current access method is checked.
3.

When the access to the shared memory units 30 and 31 is performed by the connection-type access method, the communication controller 140 calculates the average value t _a-av of the calculated access time to the shared memory units 30 and 31.
_Is compared 204 with _a preset value t _a-th ,
If ta _-av > ta _-th , switch to the connectionless access method 205.

When the access to the shared memory units 30 and 31 is performed by the connectionless access method, the communication control controller 140 calculates the average value t of the calculated access time to the shared memory units 30 and 31.
A comparison is made 206 between _a-av and a preset value t _a-th , and if t _a-av <t _a-th , the connection is switched to the connection type access method 207.

After setting the access method, start access 2
08. At the same time, the access time measurement 209 is started. Next, when the packet is returned from the shared memory unit, the access time is recorded, and the average access time is calculated 210.

FIG. 5 shows the SW in the disk I / F unit 12.
The configuration of the I / F 111 is shown. Disk I / F 1
2, two control microprocessors 105, a drive I / F 112, and a SW I / F 111 are connected via a shared bus 102. This disk I / F
Also in the unit 12, the same control as the method described in FIGS. 4 and 7 is performed in the SW I / F 111.

FIG. 6 shows S in the shared memory units 30 and 31.
The configuration of the W I / F 113 is shown. Shared memory unit 3
In 0 and 31, the memory control unit 36 and the memory module 35 are connected via the SW I / F 113.

A packet sent from the channel I / F unit 11 or the disk I / F unit 12 is decomposed into a header and transmission data by a packet decomposing unit 125, and the transmission data is stored in a buffer 135. After that, the data is sent to the memory control unit 36 through the communication control controller 141.
At the time of writing, data is written to the memory module 35, and at the time of reading, data is written to the memory module 35.
Read from Thereafter, the reply data is stored in the memory control unit 36.
From the communication controller 141. Therefore, the reply data is stored in the buffer 135. Next, the packet generation unit 120 generates a packet together with the header created by the communication control controller 141, and
/ F section.

The connection type access method has a shorter access time when the I / O throughput (low load) is lower than the connectionless type access method. But I
The ratio of the increase in the access time to the increase in the I / O throughput is large. When the I / O throughput exceeds a certain value, the access time becomes longer than in the connectionless access method. That is, the connection type access method has a limited I / O compared to the connectionless type access method.
Low throughput. Therefore, as shown in the present invention, by switching and using two shared memory access schemes having contradictory characteristics based on the access time to the shared memory unit, high I / O throughput is not impaired. Low I / O throughput (low load)
Access time can be reduced.

FIG. 10 shows a comparison between a conventional disk array device using a shared bus, a disk array control device using an interconnection network using SWs, and the shared memory access time of the disk array device of the present invention. The results are shown. The condition of the load from the host computer is based on the benchmark program PAI-IO-Drive.
r under zero-locality loading conditions (Rea
d: Write ratio is 1: 1 and cache hit rate is 0
%). The disk array controller has a channel I /
It is assumed that eight packages of the F unit 11 and 16 packages of the disk I / F unit 12 are composed of eight packages of the shared memory units 30 and 31. In the figure, the vertical axis indicates the access time to the shared memory as a relative value with the access time of the disk array control device using the shared bus at a low load being 1. Further, the horizontal axis represents the I / O throughput, and the I / O throughput of the disk array controller using the interconnection network.
It is shown as a relative value where the limit value of the / O throughput is 1. As can be seen from the figure, the disk array control device of the present invention realizes a short shared memory access time of the disk array device using the shared bus at a low load,
In addition, it is possible to realize a high I / O throughput of a disk array device using an interconnection network using SW.

In the disk array controller 2, the SW-I / F 111 in the channel I / F unit 11, the disk I / F unit 12, and the shared memory units 30 and 31, and the interconnection network 50
Due to the processing latency in SW 40 that forms
The shared memory access time is longer than that of a conventional disk array device using a shared bus. However, according to the present embodiment, when the load is low, the channel I / F unit 11 or the disk I / F unit 12 sends the shared memory unit 30, 3 or 3.
Since the path to No. 1 is established before the start of communication, the processing latency is not required except when the first path is established. Therefore, it is possible to shorten the shared memory access time when the load is low.

(Embodiment 2) Another embodiment of the present invention will be described.

In the disk array controller 2 described in the first embodiment, the shared memory unit 3 is switched from the SW I / F 111
Means are provided for directly transmitting the shared memory access method to all the via switches 0 and 31. That is, as shown in FIG. 11, the SW I / F 11 of the disk array controller 4
4 is a path 7 directly connected to the SW 42 in the interconnection network 52
0 is provided.

According to the present embodiment, it is possible to reduce the time required for transmitting the access method to the shared memory to each SW, and it is possible to further reduce the shared memory access time.

[0041]

According to the present invention, in a disk array control device using an interconnection network by SW, high I / O
It is possible to reduce the shared memory access time under low load without impairing the throughput. Thereby, I /
O The response time performance of the entire disk array controller is improved without lowering the throughput performance.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a disk array control device according to the present invention.

FIG. 2 is a diagram showing a configuration of a conventional disk array control device.

FIG. 3 is a diagram comparing the shared memory access performance (calculated value) of a disk array control device using an interconnection network with switches and a disk array control device using a shared bus.

FIG. 4 is a block diagram showing an interface unit (S) in a disk array control device according to the present invention, which is an interface unit (channel I / F unit) with a host computer and which is a switch unit;
FIG. 2 is a diagram illustrating a configuration of a W I / F).

FIG. 5 is a diagram showing a configuration of an interface (SW I / F) with a switch in an interface (disk I / F) with a plurality of magnetic disk devices in the disk array control device according to the present invention.

FIG. 6 is a diagram showing a configuration of an interface unit (SW I / F) with a switch in a shared memory unit in the disk array control device according to the present invention.

FIG. 7 is a diagram showing a flow of selecting a shared memory access method in a communication controller in the disk array control device according to the present invention.

FIG. 8 is a diagram showing a configuration of an interconnection network by switches in the disk array control device according to the present invention.

FIG. 9 is a diagram showing another configuration of an interconnection network by switches in the disk array control device according to the present invention.

FIG. 10 is a diagram comparing the shared memory access performance (calculated value) of the disk array controller according to the related art and the present invention.

FIG. 11 is a diagram showing another configuration of the disk array control device according to the present invention.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 ... Host computer, 2, 3, 4 ... Disk array control device, 11, 13 ... Interface part (channel I / F part) with a host computer, 12, 14 ... Interface part (disk I / F) with several magnetic disk devices / F section), 21... A plurality of magnetic disk devices, 30, 3
1, 32: shared memory unit, 35: memory module, 3
6 ... Memory control unit, 40, 41, 42 ... Switch, 5
0, 51, 52... Interconnection network using switches, 60.
Shared bus, 100, 105 ... microprocessor, 10
1, 102: shared bus; 110: data transmission / reception control unit (host I / F) with host computer, 111, 1
13, 114 ... Switch interface unit (SW
I / F), 112: data transmission / reception control unit (drive I / F) with a plurality of magnetic disk devices, 120: packet generation unit, 125: packet disassembly unit, 130: timer,
131 ... access method control unit, 135 ... buffer, 14
0, 141: Communication control controller.

Claims (5)

[Claims] 1. A disk array control device comprising: an interface unit with a host computer; an interface unit with a plurality of magnetic disk devices; and a shared memory unit for storing data and control information. An interface unit with the plurality of magnetic disk devices;
A disk array control device, comprising: an interconnection network for coupling the shared memory unit with a switch using a switch. A means for calculating an average value of an access time to the shared memory unit in an interface unit with the host computer and an interface unit with the plurality of magnetic disk devices; and an average value of the access time. 2. A disk array control device according to claim 1, further comprising means for storing information for controlling said switch of said interconnection network in data transferred to said shared memory unit in response to a request. 3. The switch of the interconnecting network comprises a plurality of transit switches, wherein the interconnecting network is connected to the shared network according to information for controlling the switch stored in the transfer data. 3. The disk array control device according to claim 2, further comprising control means for controlling said plurality of transit switches so as to form a transfer path of said transfer data to a memory unit. 4. The transfer means for forming a transfer path of the transfer data to the shared memory unit before transferring the transfer data, according to information for controlling the switch stored in the transfer data. And controlling the plurality of transit switches so that the formed transfer path is occupied until the shared memory access is completed, or forming a transfer path of the transfer data to the next transit switch, and 4. The disk array control device according to claim 3, further comprising means for switching whether to control the plurality of transit switches so as to release the formed transfer path when the transfer to the transit switch is completed. . 5. A method for controlling a disk array control device, wherein an interface unit with a host computer, an interface unit with a plurality of magnetic disk devices, and a shared memory unit are connected by an interconnection network using a plurality of switches. Calculating an average value of the access time to the shared memory unit from the interface unit with the host computer and the interface unit with the plurality of magnetic disk devices, and according to the average value of the access time, Storing information for controlling the plurality of switches of the interconnection network in data to be transferred to, and transferring the transfer data according to the information for controlling the plurality of switches stored in the transferred data; To form a transfer path for the transfer data to the shared memory section, and the shared memory access ends. Controlling the plurality of switches so that the formed transfer path is occupied, or forming a transfer path of the transfer data to the next switch, and when the transfer to the next switch is completed, the A method for controlling a disk array control device, comprising: switching whether to control the plurality of transit switches so as to release a formed transfer path.