JP2000250712A - Disk array controller - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a disk array controller which reduces access time from an interface part with a host computer and an interface part with a magnetic disk drive to a cache memory part and has high data transfer throughput. SOLUTION: A channel IF part 11 and a disk IF part 12 are connected to cache memory part 14 through a selector part 13. When accesses of a prescribed number or more from the part 11 or 12 compete, the part 3 selects the prescribed number of access paths. Respective microprocessors in the parts 11 and 12 are connected to a memory controller 105 in the part 14 with a control line, and the controller 105 performs an arbitration operation occurring in the part 13. Thus, it is possible to reduce waiting time due to access contention.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a control device for a disk array device which stores data in a plurality of magnetic disk devices.

[0002]

2. Description of the Related Art The I / O performance of a disk subsystem using a magnetic disk as a storage medium (hereinafter referred to as "subsystem") is compared with the I / O performance of a main storage of a computer using a semiconductor storage device as a storage medium. Is about three to four digits smaller,
Efforts have conventionally been made to reduce this difference, that is, to improve the I / O performance of the subsystem. As one method for improving the I / O performance of a subsystem, a subsystem is configured by a plurality of magnetic disk devices,
2. Description of the Related Art There is known a system called a disk array in which data is stored in a plurality of magnetic disk devices.

FIG. 2 shows a configuration of a conventional disk array. A plurality of channel IF units 11 for executing data transfer between the host computer 50 and the disk array control device 2, and a plurality of disk IF units 1 for executing data transfer between the magnetic disk device 20 and the disk array control device 2
2, a cache memory unit 14 for temporarily storing data of the magnetic disk device 20, and control information on the disk array control device 2 (for example, data transfer between the channel IF unit and the disk IF unit and the cache memory unit 14). A shared memory unit 15 for storing information related to control, and a cache memory unit 14 and a shared memory unit 15.
Is configured to be accessible from all channel IF units 11 and disk IF units 12. In this disk array, a one-to-one connection is made between the channel IF unit 11 and the disk IF unit 12 and the shared memory unit 15 and between the channel IF unit 11 and the disk IF unit 12 and the cache memory unit 14. .

The channel IF unit 11 has an interface for connecting to the host computer 50 and a microprocessor (not shown) for controlling input and output to and from the host computer 50. Also, disk IF
The unit 12 has an interface for connecting to the magnetic disk device 20 and a microprocessor (not shown) for controlling input and output to and from the magnetic disk device 20. The disk IF unit 12 also executes a RAID function.

FIG. 3 shows the configuration of another conventional disk array. A plurality of channel IF units 11 for executing data transfer between the host computer 50 and the disk array controller 3, and a plurality of disk IF units 1 for executing data transfer between the magnetic disk device 20 and the disk array controller 3
2, a cache memory unit 14 for temporarily storing data of the magnetic disk device 20, and control information relating to the disk array controller 3 (for example, data transfer between the channel IF unit and the disk IF unit and the cache memory unit 14). A shared memory unit 15 for storing control-related information). Each of the channel IF unit 11 and the disk IF unit 12 and the shared memory unit 15 are connected by a shared bus 130, and each of the channel IF unit 11 and the disk IF unit 12 is connected to the cache memory. The units 14 are connected by a shared bus 131.

[0006]

In response to demands for higher performance of the disk array system, a large-scale disk array control device and a high-speed component have been used, for example, a processor in the channel IF section and the disk IF section. It has responded by increasing the number and cache memory capacity, applying high-performance processors, expanding the internal bus width, and improving the bus transfer capability. However, in the prior art shown in FIG. 3, it is becoming difficult for the transfer capability of the internal bus to follow the enlargement and performance improvement of the system.

In order to improve the internal bus performance and obtain a high memory access performance, a 1: 1 connection between the channel IF unit and the disk IF unit and the cache memory and the shared memory as in the prior art shown in FIG. There is a method of connecting to. According to this method, the internal bus performance increases in proportion to the number of access paths connected to the memory. However, in proportion to the increase in the number of mounted processors, access requests to the shared memory and the cache memory also increase. Therefore, in order to maximize the internal bus performance, each channel IF unit, disk IF unit-shared memory,
It is necessary to efficiently control access between cache memories.

An object of the present invention is to solve the above-mentioned problems, to provide a disk array control device which efficiently uses an access path between a channel IF unit, a disk IF unit and a cache memory and has a high data transfer throughput to a cache memory. To provide.

[0009]

SUMMARY OF THE INVENTION The object of the present invention is to provide a disk drive and a plurality of channel interface units each having an interface with a host computer and a microprocessor for controlling input / output to and from the host computer. And a plurality of disk interface units having a microprocessor for controlling input / output to and from the disk device, and temporarily store data stored in the disk device connected to the interface with the disk device. A cache memory unit having a memory module, a memory controller controlling access to the memory module, the plurality of channel interface units, the plurality of disk interface units, and connection to the cache memory unit A selector unit for executing an access request from the plurality of channel interface units and the plurality of disk interface units to the cache memory unit, and a microprocessor in the plurality of channel interface units and the plurality of disk interface units, A disk array controller having a plurality of control lines connecting the memory controller.

Preferably, the memory controller comprises:
Means for receiving an access request from each of the microprocessors in the plurality of channel interface units or the plurality of disk interface units via the plurality of control lines, and performing arbitration when the access requests conflict.

The above object is also achieved by providing a plurality of channel interface units each having an interface unit with a host computer, a microprocessor for controlling input / output with respect to the host computer, and an interface unit with a disk device. A plurality of disk interface units having a microprocessor that controls input and output to the disk device, and a memory module that temporarily stores data stored in the disk device connected to the interface with the disk device; A cache memory unit having a memory controller that controls access to the memory module, the plurality of channel interface units, the plurality of disk interface units, and the cache memory unit; A plurality of channel interface units and a selector unit for executing an access request from the plurality of disk interface units to the cache memory unit, wherein each channel interface unit of the plurality of channel interface units is connected to the cache memory unit. A cache memory access controller for controlling access; each of the plurality of disk interface units having a cache memory access controller for controlling access to the cache memory unit; Connecting the cache memory access control unit of each channel interface unit, the cache memory access control unit of each disk interface unit of the plurality of disk interface units, and the memory controller It is achieved by the disk array controller and having a plurality of control lines that.

Preferably, the memory controller comprises:
Means for receiving an access request from each of the plurality of channel interface units or the respective cache memory access control units in the plurality of disk interface units via the plurality of control lines, and performing arbitration when the access requests conflict. Have.

The above object is also achieved by providing a plurality of channel interface units each having an interface unit with a host computer, a microprocessor for controlling input / output with respect to the host computer, and an interface unit with a disk device. A plurality of disk interface units having a microprocessor that controls input and output to the disk device, and a memory module that temporarily stores data stored in the disk device connected to the interface with the disk device; A cache memory unit having a memory controller that controls access to the memory module, the plurality of channel interface units, the plurality of disk interface units, and the cache memory unit; A selector unit for executing an access request from the plurality of channel interface units and the plurality of disk interface units to the cache memory unit; respective microprocessors in the plurality of channel interface units and the plurality of disk interface units; and the selector unit And a plurality of control lines for connecting to the disk array controller.

Preferably, the selector unit receives an access request from each of the plurality of microprocessors in the plurality of channel interface units or the plurality of disk interface units via the plurality of control lines, and the access requests compete with each other. In some cases, a means for arbitration is provided.

[0015]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be described in detail below.

(Embodiment 1) FIG. 1 shows an embodiment of the present invention.

FIG. 1 shows an embodiment of the present invention.

The disk array controller 1 has two interface units (channel IF units) 11 with the host computer 50, two interface units (disk IF units) 12 with the magnetic disk device 20, and two selector units 13 , Two cache memory units 14, two shared memory units 15, access paths 0: 135, access paths 1: 136, and access paths 2: 137.

The configuration of the channel IF unit 11 will be described with reference to FIG. The channel IF unit 11 includes two IFs (host IFs) 102 with the host computer 50, two microprocessors 101 for controlling input / output to and from the host computer 50, and an access control unit for controlling access to the cache memory unit 14. (CM access control unit) 104, and executes data transfer between the host computer 50 and the cache memory unit 14. The microprocessor 101 and the host IF 102 are connected to the internal bus 10
6 and the CM access control unit 104 is directly connected to the two host IFs 102. Between the two microprocessors 101 and the memory controller,
They are connected by a control line 216.

The disk IF unit 12 has the same configuration as the channel IF unit 11 described with reference to FIG. Disk IF
The unit 12 includes two IFs (drive IFs) 103 for the magnetic disk device 20, two microprocessors 101 for controlling input / output to the magnetic disk device 20, and one access control unit (CM) for the cache memory unit 14.
Access control unit) 104, and the magnetic disk device 20
And data transfer between the cache memory unit and the cache memory unit.
The microprocessor 101 and the drive IF 103 are connected by an internal bus 106, and the CM access control unit 1
04 is directly connected to the two drive IFs 103. The two microprocessors 101 and the memory controller are connected by a control line 216. Also,
The disk IF unit also executes a RAID function.

Here, the above number is just an example, and the number is not limited to the above.

The cache memory unit 14 has a memory controller 105 and a memory module 106, and stores data to be recorded on the magnetic disk device 20, the data, management information in the system, and the like.

When accessing the cache memory unit 14, the microprocessor 101 sends an access request to the memory controller 105 using the control line 6: 216. The memory controller 105 performs arbitration based on an access request from each of the microprocessors 101, and returns access approval to the microprocessor 101 that has acquired the right to access the memory using the control line 6: 216. When the microprocessor 101 receives access approval from the memory controller 105, the microprocessor 101 starts accessing the cache memory unit 14.

The selector section 13 has two channel IFs.
A total of four access paths 0: 135 are connected, one each from the unit 11 and the two disk IF units 12. Further, the selector unit 13 has one access path 1: 136 to each of the two cache memory units 14 for a total of two access paths.
The book is connected.

Since the number of paths is as described above between the access paths 0: 135 and 1: 136, the selector 13 has four access paths from the channel IF 11 and the disk IF 12. It has a function of selecting and executing only two of the requests from 0: 135 corresponding to the number of access paths 1: 136 to the cache memory unit 14.

Here, the above number is merely an example, and the number is not limited to the above. One selector unit 1
3 and the number of access paths connected to the cache memory unit 14 by the channel IF unit 11 and the disk IF unit 12.
If the number is set to be smaller than the number of access paths connected to one selector unit 13 and the number of selector units 13 is smaller than the total number of the channel IF unit 11 and the disk IF unit 12, the cache memory The number of access paths connected to the unit 14 can be reduced. When the problem of the LSI pin neck of the cache memory section 14 and the connector neck of the package occurs, the above-described manner can eliminate the pin neck of the LSI and the connector neck of the package.

FIG. 6 shows a configuration inside the CM access control unit 104. The CM access control unit 104 includes a selector 302, a path IF 301 for access paths 0: 135 connected to the cache memory unit 14, a data error check unit 300, and a data transfer control unit 310. Two ports of the selector 302 are connected to the host IF 102 or the drive IF 103 via the data line 210. Another port of the selector 302 is connected to the path IF 301. The path IF 301 is connected to the selector unit 13 via access paths 0: 135. The data transfer control unit 310 controls the host IF 10
2 or drive IF 103, and control line 2:
The connection 212 is connected to the data transfer control unit 310 in the selector unit 13. Further, the data transfer control unit 310 switches the selector 302.

FIG. 8 shows the configuration inside the selector section 13. The selector section 13 connects the path IF 301 to the access path 0: 135 connected to the channel IF section 11 or the disk IF section 12 and the path IF 301 to the access path 0: 136 connected to the cache memory section 14, and connects the two to each other. Selector 304, the data error check unit 300, and the address (ad) for analyzing the address and command sent from the CM access control unit 104.
r), a command (cmd) analysis unit 305, and a data transfer control unit 310. The data transfer control unit 310 is connected to the data transfer control unit 310 in the CM access control unit 104 by the control line 2: 212, and is connected to the data transfer control unit 310 in the memory controller 105 of the cache memory unit 14 by the control line 4: 214. Connected to. Further, the data transfer control unit 310 switches the selector 304.

FIG. 10 shows the configuration inside the cache memory unit 14. The cache memory unit 14 has a memory controller 105 and a memory module 106.
The memory controller 105 includes a path IF 301 to the access path 1: 136 connected to the selector unit 13, a memory IF 308 to the memory module 106, a selector 302 to connect them to each other, a data error check unit 300, Memory control unit 307 for controlling access to CM 106 and CM access control unit 1
The address (adr) for analyzing the address and the command sent from the address 04, the command (cmd) analyzer 305
, An arbiter 306 and a data transfer control unit 310. The arbiter 306 is connected to each microprocessor 101 by control lines 6: 216. Data transfer control unit 31
0 is connected to the data transfer control unit 310 in the selector unit 13 by a control line 4: 214. Further, the data transfer control unit 310 switches the selector 302.

Next, a procedure for accessing the cache memory unit 14 will be described. When accessing the cache memory unit 14, the microprocessor 101 in the channel IF unit 11 or the disk IF unit 12 sends the message to the memory controller 10 of the cache memory unit 14 to be accessed.
The access request is sent to the arbiter 306 in the control line 5 using the control line 6: 216.

Arbiter 3 in memory controller 105
06 selects one of the access requests from each microprocessor 101 by arbitration.

In the configuration of this embodiment (FIG. 1), when the cache memory unit 14 is accessed, the CM access control unit 1
04, selector section 13, and memory controller 105
Since access conflicts occur at three locations, it is necessary to perform arbitration at each location to resolve the conflict. A feature of the present invention is that these three arbitrations are performed by the arbiter 306 in the memory controller 105.
It is to perform collectively. This makes it possible to reduce the three waiting times due to access contention to one.

The arbiter 306 sends a control line 6: 2 to the microprocessor 101 which has issued the selected access request.
Use 16 to return access authorization. The microprocessor 101 that has received the access approval is the host IF 102
Alternatively, the cache memory unit 1
4 is started.

Host IF 1 receiving access start instruction
02 or the drive IF 103 is connected to the control line 1: 211
Sends a signal indicating the start of access to the data transfer control unit 310 in the CM access control unit 104 and a signal indicating the memory controller 105 to be accessed. The data transfer control unit 310 determines which one of the two control lines 1: 211 has received the access start signal,
2 and the host IF 10
2 or the drive IF 103, and returns a signal of access approval to the selector unit 1 by the control line 2: 212.
A signal indicating the start of access and a signal indicating the memory controller 105 of the access destination are output to the data transfer control unit 310 in the third section.

In this embodiment, the CM access control unit 104
Two host IFs 102 or two drive IFs
103 is connected. However, CM access control unit 1
Since there is only one access route from the memory controller 105 to the memory controller 105, when the memory controller 105 has a function of simultaneously processing a plurality of accesses to the memory module 106, the memory controller 105 is connected to the same CM access control unit 104 during arbitration by the arbiter 306. 2
It is necessary not to grant access authorization to both the two host computers 101 or the two microprocessors 101 controlling the two drive interfaces. Host IF 102 or drive IF connected to CM access control unit 104
If the number of access routes 103 is equal to the number of access routes from one CM access control unit 104 to one memory controller 105, this is not the case.

In this embodiment, the memory controller 1
05 is two, whereas the number of access paths 0: 135 connected to the CM access control unit 104 is one.
Two memory controllers 1 from the access control unit 104
05 cannot be accessed at the same time. Therefore, the two memory controllers 105 are connected by a control line, and the arbiter 30 in one memory controller 105 is connected.
At the time of arbitration in step 6, both the two host IFs connected to the same CM access control unit 104 or the two microprocessors 101 controlling the two drive IFs are referred to by referring to the information of the arbiter 306 in the other memory controller 105. Must not be given access authorization. This is not the case when it is possible to simultaneously access the two memory controllers 105 from the CM access control unit 104.

In the present embodiment, the arbiter 306 does not perform arbitration in consideration of the above-mentioned restrictions, and the two host IFs 1 connected to the same CM access control unit 104 do not perform arbitration.
02 or two microprocessors 101 controlling the two drive IFs 103 perform exclusive control so that the CM access control unit 104 is not used at the same time. That is, the two microprocessors 101 perform exclusive control so as not to simultaneously issue an access request to the cache memory unit 14.

Therefore, the data transfer control section 310 regards an access start signal from both of the two control lines 1: 211 as an error and performs a fault handling.

The host IF 102 or the drive IF 1
03 sends an address, a command, and data (only at the time of writing data) through the data line 210 upon receiving the access approval. The CM access control unit 104 transmits the transmitted address, command, and data (only at the time of data writing) via the selector 302 and the path IF 301.
The data is transmitted to the access path 0: 135 connected to the selector unit 13.

Data transfer control section 31 in selector section 13
0, upon receiving an access start signal and a signal indicating the memory controller 105 to be accessed by the control line 2: 212, which of the four control lines 2: 212 has received the access start signal and the access destination The selector 304 is switched by the signal indicating the memory controller 105 of the CM controller 105, and the CM access controller 10 is controlled by the control line 2: 212.
4 and a signal indicating the start of access to the data transfer control unit 310 in the memory controller 105 via the control line 4: 214, and a signal indicating the start of access to the data transfer control unit 310 in the memory controller 105.
A signal indicating 5 is issued.

In this embodiment, since there is only one access path 1: 136 between the selector unit 13 and one memory controller 105, the channel IF unit 11 and the disk IF unit connected to the same selector unit 13 during arbitration by the arbiter 306. Microprocessor 1 in unit 12
Only one of 01 needs to be granted access approval. If there are a plurality of access paths 1: 136 between the selector unit 13 and one memory controller 105 and the memory controller 105 can simultaneously process requests equal to the number of the access paths, access is granted to the microprocessors 101 of the same number. Can be given.

To perform the above-described control, the data transfer control unit 310 generates an error when an access start signal from a plurality of the four control lines 2: 212 to the same memory controller 105 is received. Deemed and perform failure processing.

The selector unit 13 transmits the transmitted address, command, and data (only at the time of writing data) to the path IF 301 connecting to the access paths 0 and 135, the selector 304, and the path IF 3 connecting to the access paths 1: 136.
01 to the access path 1: 136 connected to the memory controller 105.

The transmitted address and command are sent to the memory controller 105 and are also taken into the address (adr) and command (cmd) analyzer 305 to determine which of the two memory controllers 105 is to be accessed. The signal is checked and compared with a signal indicating the memory controller 105 to which the control line 212 is accessed.

Here, when the signal indicating the memory controller 105 to be accessed is not transmitted by the control line as described above, the host IF 102 or the drive IF 103
Sends only the address and command first. The address (adr) in the selector unit 13 and the command (cmd) analysis unit 305 check the access destination memory controller 105 and switch the selector 304, and then the access approval is returned via the CM access control unit 104. After confirming the above, it is necessary to perform processing in a procedure of transmitting data.

When the data transfer control unit 310 in the memory controller 105 receives a signal for starting access via the control line 4: 214 and a signal indicating the memory controller 105 to be accessed, the data transfer control unit 310 selects one of the two control lines 4: 214. Selector 3 depending on whether an access start signal is received from
02, and the selector unit 1 is controlled by the control line 4: 214.
3 and returns an access approval signal to the data transfer control unit 310 and a signal indicating the start of access to the memory control unit 307.

In order to perform the above-described control, the data transfer control unit 310 regards an access start signal from both of the two control lines 4: 214 as an error, and performs fault handling.

The transmitted address and command are taken into the address (adr) / command (cmd) analysis unit 305, and control information of the memory obtained as a result of the analysis is sent to the memory control unit 307. Further, the access destination memory controller 105 is checked, and if it is different from the own memory controller, it is regarded as an error and a fault process is performed.

At the time of writing data, access path 1:
136, the data sent through the path IF 301,
The data is written to the memory module 106 via the selector 302 and the memory IF 308. When reading data, the data is read from the memory module 106 and the memory IF
308, the selector 302, and the path IF301 to the access path 1: 136.

When the access to the memory module 106 is completed, the data transfer control unit 310 generates a status indicating the access status, and sends the status to the host IF 102 or the drive IF 103 via the selector unit 13 and the CM access control unit 104. .

In this embodiment, the CM access control unit 104
After switching the selector 302, the data transfer control unit 310 sends an access start signal to the selector unit 13 and returns an access approval to the host IF 102 or the drive IF 103. In such a case, the host I
Before the address is sent from the F102 or the drive IF 103, the processing time of each unit must be set so that the access approval is returned from the selector unit 13. Similarly, in the selector unit 13, the processing time of each unit must be set so that an access approval is returned from the memory controller 105 before the address is sent from the CM access control unit 104. If this is not possible, a buffer may be provided in the CM access control unit 104 and the selector unit 13 or the selector unit 1
No. 3 does not return the access approval to the CM access control unit 104 until the access approval is returned from the memory controller 105. Similarly, the CM access control unit 104 returns the host IF 10 until the access approval is returned from the selector unit 13.
2 or drive IF 103 must not be returned.

As described above, arbitration for resolving conflicts occurring in three places is performed by the memory controller 10.
5, the waiting time for three times due to access contention can be reduced to one time. As a result, the access time to the cache memory unit 14 is reduced, and high-throughput data transfer can be realized.

Further, as shown in FIG.
Unit 11, disk IF unit 12, cache memory unit 14
This embodiment is also effective in the disk array control device 1 in which the CM access control unit 10 is connected to the disk array control device 1 through the interconnection network 110 constituted by four switches (SW) 16.
4, arbitration for resolving access conflicts occurring in each of the SW 16 and the memory controller 105 can be collectively performed by the memory controller 105. As a result, the access time to the cache memory unit 14 is reduced, and high-throughput data transfer can be realized.

(Embodiment 2) FIG. 4 shows another embodiment of the present invention.

The disk array control device 1 has a channel I
It has an F unit 11, a disk IF unit 12, a selector unit 13, and a cache memory unit 14, and access paths 0: 135 and 1: 136.

Channel IF section 11, Disk IF section 1
2 and the configuration of the selector unit 13 are the same as in the first embodiment.

The CM access control unit 104 and the memory controller 105 are connected by a control line 3: 213. CM
When accessing the cache memory unit 14, the access control unit 104 sends an access request to the memory controller 105 using the control line 3: 213. The memory controller 105 performs arbitration based on the access request from each CM access control unit, and sends the arbitration to the CM access control unit 104 that has acquired the right to access the memory.
An access approval is returned using control line 3: 213. CM
Upon receiving the access approval from the memory controller 105, the access control unit 104 starts accessing the cache memory unit 14.

FIG. 7 shows the configuration inside the CM access control unit 104. The CM access control unit 104 includes a selector 302, a path IF 301 of access paths 0: 135 connected to the cache memory unit 14, and a packet buffer 30 for temporarily storing addresses, commands, and data.
3, a data error check unit 300 and a data transfer control unit 310. Two ports of the selector 302 are connected to the host IF 102 or the drive IF 103 via the data line 210. Another port of the selector 302 is connected to the path IF 301. Path IF
Reference numeral 301 denotes an access path 0: 135 connected to the selector unit 13. The data transfer control unit 310 has a control line 1:21
1 is connected to the host IF 102 or the drive IF 103, the control line 2: 212 is connected to the data transfer control unit 310 in the selector unit 13, and the control line 213 is connected to the data transfer control unit 310 in the memory controller 105. . Further, the data transfer control unit 310 switches the selector 302.

The configuration inside the selector section 13 is the same as the configuration of the first embodiment shown in FIG.

The configuration in the cache memory unit 14 is shown in FIG.
In the configuration of the first embodiment shown in FIG. 0, the control line 3: 213 connected to the data transfer control unit 310 in the CM access control unit 104 is replaced by the arbiter 306 instead of the control line 6: 216.
Connected.

Next, a procedure for accessing the cache memory unit 14 will be described. When accessing the cache memory unit 14, the microprocessor 101 in the channel IF unit 11 or the disk IF unit 12
It instructs F102 or the drive IF 103 to start accessing the cache memory unit 14.

The host IF 1 receiving the access start instruction
02 or the drive IF 103 is connected to the control line 1: 211
Sends a signal indicating the start of access to the data transfer control unit 310 in the CM access control unit 104 and a signal indicating the memory controller 105 to be accessed.
The address, command, and data are transmitted through the data line 210.

The CM access control unit 104 controls the data line 2
The address, command, and data (only when writing data) transmitted through the
To be stored temporarily. The data transfer control unit 310 performs arbitration, and executes the two host IFs 102 or 2
It is determined which of the two drive IFs is given an access right to the cache memory unit 14. afterwards,
The cache memory unit 14 accessed by the host IF 102 or the drive IF 103 to which the access right has been given.
An access request is sent to the arbiter 306 in the memory controller 105 using the control line 3: 213.

Arbiter 3 in memory controller 105
06 selects one of the access requests from each CM access control unit 104 by arbitration.

In the configuration of this embodiment (FIG. 1), when the cache memory unit 14 is accessed, the CM access control unit 1
04, selector section 13, and memory controller 105
Since access conflicts occur at three locations, it is necessary to perform arbitration at each location to resolve the conflict. The feature of the present invention is that the arbitration at the selector unit 13 and the memory controller 105 is performed by the arbiter 3 in the memory controller 105.
06. This makes it possible to reduce the three waiting times due to access contention to two.

In this embodiment, as in the first embodiment, it is impossible to connect the control lines 6: 216 from all the microprocessors 101 to the memory controller 105 due to the pin-neck of the LSI mounting the memory controller 105. It is effective for

The arbiter 306 sends a control line 3: 2 to the CM access control unit 104 which has issued the selected access request.
13 to return access authorization.

The data transfer control unit 310 in the CM access control unit 104 having received the access approval is
Is switched, and the selector unit 13 is controlled by the control line 2: 212.
A signal indicating the start of access to the data transfer control unit 310 and a signal indicating the memory controller 105 of the access destination are output. When the access approval is returned from the selector unit 13, the address, command, and data (only at the time of writing) in the packet buffer are transferred to the selector 302 and the path IF 301.
Through the access path 0: 135. The subsequent processing procedure is the same as the procedure described in the first embodiment.

In this embodiment, since there is only one access path 1: 136 between the selector unit 13 and one memory controller 105, at the time of arbitration by the arbiter 306, the CM access control unit 104 connected to the same selector unit 13 Needs to be granted access authorization to only one of them. If there are a plurality of access paths 1: 136 between the selector unit 13 and one memory controller 105, and the memory controller 105 can simultaneously process requests equal to the number of the access paths, the CM access control units 104 of the same number are sent to the same number. Access authorization can be given.

In this embodiment, as in the first embodiment,
Before the selector unit 13 receives the address from the CM access control unit 104, the memory controller 1
The processing time of each unit must be set so that the access approval is returned from 05. If this is not possible, a buffer must be provided in the selector unit 13 or the selector unit 13 must not return an access approval to the CM access control unit 104 until an access approval is returned from the memory controller 105. .

If the control lines from all the microprocessors 101 cannot be connected to the memory controller 105 due to the LSI pin neck, as described above, the conflict between the selector unit 13 and the memory controller 105 is eliminated. By performing arbitration collectively in the arbiter 306 in the memory controller 105, it is possible to reduce three waiting times due to access contention to two times. As a result, the access time to the cache memory unit 14 is reduced, and high-throughput data transfer can be realized.

(Embodiment 3) FIG. 5 shows another embodiment of the present invention.

The disk array control device 1 has a channel I
It has an F unit 11, a disk IF unit 12, a selector unit 13, and a cache memory unit 14, and access paths 0: 135 and 1: 136.

Channel IF section 11 and disk IF section 1
The configuration of the second embodiment is the same as that of the first embodiment.

Microprocessor 101 and selector unit 1
3 are connected by a control line 5: 215. When accessing the cache memory unit 14, the microprocessor 101 sends an access request to the selector unit 13 using the control line 5: 215. The selector unit 13 performs arbitration based on an access request from each of the microprocessors 101, and returns an access acknowledgment using the control line 5: 215 to the microprocessor 101 that has acquired the right to access the memory. Microprocessor 101
Starts access to the cache memory unit 14 upon receiving access approval from the selector unit 13.

The internal configuration of the CM access control unit 104 is as follows.
This is the same as the configuration of the first embodiment shown in FIG.

FIG. 9 shows the configuration inside the selector section 13. The selector unit 13 connects the path IF 301 with the access path 0: 135 connected to the channel IF unit 11 or the disk IF unit 12 and the path IF 301 with the access path 1: 136 connected to the cache memory unit 14. Selector 304, a data error check unit 300, an address (adr) for analyzing addresses and commands sent from the channel IF unit 11 or the disk IF unit 12, a command (cmd) analyzing unit 305, and an arbiter 306. , Data transfer control section 310
Having. The data transfer control unit 310 controls the control line 2:21.
2. Data transfer control unit 3 in CM access control unit 104
10 and connected to the data transfer control unit 310 in the memory controller 105 of the cache memory unit 14 by the control line 4: 214. Also, the data transfer control unit 310
Switches the selector 304. Arbiter 306
Control line 5:21 from the microprocessor 101
5 is connected. In the present embodiment, the channel IF unit 11,
Alternatively, an access path 0: 1 connected to the disk IF unit 12
35, the number of IF ports 301 is four, and the path IFs to access paths 1: 136 connected to the cache memory unit 14.
The number of 301s was two. As in the case of the first embodiment, the above number is merely an example, and the number is not limited to the above.

FIG. 11 shows the configuration inside the cache memory unit 14. The cache memory unit 14 has a memory controller 105 and a memory module 106.
The memory controller 105 includes a path IF 301 to the access path 1: 136 connected to the selector unit 13, a memory IF 308 to the memory module 106, a selector 302 connecting the two, and a packet buffer for temporarily storing addresses, commands, and data. 303, a data error check unit 300, and a memory module 106
Memory control unit 307 for controlling access to the address, address (adr) for analyzing the address and command sent from CM access control unit 104, and command (cmd)
An analysis unit 305 and a data transfer control unit 310 are provided. The data transfer control section 310 is connected to the data transfer control section 310 in the selector section 13 by a control line 4: 214. Further, the data transfer control unit 310 switches the selector 302. In the present embodiment, the number of path IFs 301 for the access path 1: 136 connected to the selector unit 13 is two. The above number is merely an example, and the number is not limited to the above.

Next, a procedure for accessing the cache memory unit 14 will be described. When accessing the cache memory unit 14, the microprocessor 101 in the channel IF unit 11 or the disk IF unit 12 sends the microprocessor 101 to the arbiter 306 in the selector unit 13 connected to the channel IF unit 11 or the disk IF unit 12 in which the microprocessor 101 is mounted. , Using the control line 5: 215.

The arbiter 306 in the selector section 13 is adapted to arbitrate the respective microprocessors 101.
Select one of the access requests from.

In the configuration of this embodiment (FIG. 1), when the cache memory unit 14 is accessed, the CM access control unit 10
4, access conflicts occur at three locations: the selector unit 13 and the memory controller 105. Therefore, arbitration must be performed at each location to eliminate the conflict. The feature of the present invention resides in that the arbitration in the CM access control unit 104 and the selector unit 13 is performed by the arbiter 306 in the selector unit 13 collectively. As a result, 3
Waiting time can be reduced to two times.

This embodiment is different from the first embodiment in that it is impossible to connect the control lines 6: 216 from all the microprocessors 101 to the memory controller 105 due to the pin-neck of the LSI mounting the memory controller 105. It is effective for However, the path IF 301 between the selector 304 in the selector unit 13 and the access path 1: 136
Or the path IF in the memory controller 105
It is necessary to provide a packet buffer 303 between the selector 302 and the packet buffer 303. In this embodiment, the memory controller 105
, A packet buffer 303 is provided.

The reason why the packet buffer 303 is provided as described above is that the selector unit 13 uses the cache memory unit 1.
This is because even if the right to use the access path 1: 136 connected to No. 4 is acquired, contention for access to the memory module 106 occurs in the memory controller 105 and a waiting time occurs. Therefore, if the packet buffer 303 is not provided, the microprocessor 101 cannot start accessing the cache memory unit 14 until the right to access the memory module 106 can be obtained. During that time, the access paths 0: 135 and 1: 136 Will be occupied. Therefore, the use efficiency of the access path is reduced, and the data transfer throughput is reduced.

The arbiter 306 sends a control line 5: 2 to the microprocessor 101 which has issued the selected access request.
Use 15 to return access authorization. The microprocessor 101 that has received the access approval is the host IF 102
Alternatively, the cache memory unit 1
4 is started.

Host IF 1 receiving access start instruction
02 or the drive IF 103 is connected to the control line 1: 211
Sends a signal indicating the start of access to the data transfer control unit 310 in the CM access control unit 104 and a signal indicating the memory controller 105 to be accessed. The data transfer control unit 310 determines which one of the two control lines 1: 211 has received the access start signal,
2 and the host IF 10
2 or the drive IF 103, and returns a signal of access approval to the selector unit 1 by the control line 2: 212.
A signal indicating the start of access and a signal indicating the memory controller 105 of the access destination are output to the data transfer control unit 310 in the third section.

In this embodiment, the CM access control unit 104
Two host IFs 102 or two drive IFs
103 is connected, CM access control unit 104
Since there is only one access route from the arbiter 306 to the selector unit 13, the two host IFs connected to the same CM access control unit 104 during arbitration by the arbiter 306.
Alternatively, it is necessary not to give access approval to both of the two microprocessors 101 controlling the two drive IFs. When the number of host IFs 102 or drive IFs 103 connected to the CM access control unit 104 is equal to the number of access routes to the selector unit 13,
This is not the case.

When arbitration is not performed by the arbiter 306 in consideration of the above-described restrictions, two microprocessors 101 controlling two host IFs 102 or two drive IFs 103 connected to the same CM access control unit 104 perform exclusive control. Therefore, it is necessary to prevent the CM access control unit 104 from being used at the same time.

When the above-described control is performed, the data transfer control section 310 regards an access start signal from both of the two control lines 1: 211 as an error and performs a fault handling.

The host IF 102 or the drive IF 1
03 sends an address, a command, and data (only at the time of writing data) through the data line 210 upon receiving the access approval. The CM access control unit 104 transmits the transmitted address, command, and data (only at the time of data writing) via the selector 302 and the path IF 301.
The data is transmitted to the access path 0: 135 connected to the selector unit 13.

Data transfer control section 31 in selector section 13
0, upon receiving an access start signal and a signal indicating the memory controller 105 to be accessed by the control line 2: 212, which of the four control lines 2: 212 has received the access start signal and the access destination The selector 304 is switched by the signal indicating the memory controller 105 of the CM controller 105, and the CM access controller 10 is controlled by the control line 2: 212.
4 and a signal indicating the start of access to the data transfer control unit 310 in the memory controller 105 via the control line 4: 214, and a signal indicating the start of access to the data transfer control unit 310 in the memory controller 105.
A signal indicating 5 is issued.

The selector unit 13 sends the transmitted address, command, and data (only at the time of data writing) to the path IF 301 connected to the access paths 0 and 135, the selector 304, and the path IF 3 connected to the access paths 1: 136.
01 to the access path 1: 136 connected to the memory controller 105.

The transmitted address and command are sent to the memory controller 105, and are also taken into the address (adr) and command (cmd) analyzer 305 to determine which of the two memory controllers 105 is to be accessed. The signal is checked and compared with a signal indicating the memory controller 105 to which the control line 212 is accessed.

The data transfer control unit 310 in the memory controller 105 receives an access start signal on the control line 4: 214 and a signal indicating the memory controller 105 to be accessed, and receives a signal from the selector unit 13 on the control line 4: 214. A signal of access approval is returned to the data transfer control unit 310 of FIG. The transmitted address, command, and data (only when writing data) are temporarily stored in the packet buffer 303.

The data transfer control section 310 performs arbitration, and determines which of the two access paths 1: 136 is given the memory access right.

An address and a command are taken into the address (adr) and command (cmd) analyzer 305 from the packet buffer 303 on the path side to which the memory access right is given, and the control information of the memory obtained as a result of the analysis is stored in the memory controller. 307. Further, the access destination memory controller 105 is checked, and if it is different from the own memory controller, it is regarded as an error and a fault process is performed.

When writing data, the data stored in the packet buffer 303 is stored in the selector 302 and the memory I
The data is written to the memory module 106 via F308.
When reading data, the data is read from the memory module 106, and the memory IF 308, the selector 302,
The data is transmitted to the access path 1: 136 via the path IF301.

When the access to the memory module 106 is completed, a status indicating the access status is generated in the data transfer control section 310 and transmitted to the host IF 102 or the drive IF 103 via the selector section 13 and the CM access control section 104. .

In this embodiment, the CM access control unit 104
After switching the selector 302, the data transfer control unit 310 sends an access start signal to the selector unit 13 and returns an access approval to the host IF 102 or the drive IF 103. In such a case, the host I
Before the address is sent from the F102 or the drive IF 103, the processing time of each unit must be set so that the access approval is returned from the selector unit 13. If this is not possible, a buffer is provided in the CM access control unit 104 or the CM access control unit 1
In step 04, it is necessary to prevent the access approval from being returned to the host IF 102 or the drive IF 103 until the access approval is returned from the selector unit 13.

When the control lines from all the microprocessors 101 cannot be connected to the memory controller 105 due to the LSI pin-neck, as described above, the conflict resolution occurring at the two places of the CM access control unit 104 and the selector unit 13 is resolved. Arbitration for the selector unit 1
Also, the arbiter 306 within 3 can collectively reduce the waiting time of three times due to access contention to two times. As a result, the access time to the cache memory unit 14 is reduced, and high-throughput data transfer can be realized.

[0100]

According to the present invention, the access time from the channel IF section and the disk IF section to the cache memory section can be reduced. Thereby, the data transfer throughput of the disk array control device is improved.

[Brief description of the drawings]

FIG. 1 is a diagram showing a configuration of a disk array control device according to the present invention.

FIG. 2 is a diagram showing a configuration of a conventional disk array control device.

FIG. 3 is a diagram showing a configuration of a conventional disk array control device.

FIG. 4 is a diagram showing another configuration of the disk array control device according to the present invention.

FIG. 5 is a diagram showing another configuration of the disk array control device according to the present invention.

FIG. 6 shows a CM in a disk array controller according to the present invention.
The figure which shows the structure of an access control part.

FIG. 7 is a CM in the disk array control device according to the present invention.
The figure which shows the other structure of an access control part.

FIG. 8 is a diagram showing a configuration of a selector unit in the disk array control device according to the present invention.

FIG. 9 is a diagram showing another configuration of the selector unit in the disk array control device according to the present invention.

FIG. 10 is a diagram showing a configuration of a cache memory unit in the disk array control device according to the present invention.

FIG. 11 is a diagram showing another configuration of the cache memory unit in the disk array control device according to the present invention.

FIG. 12 is a diagram showing another configuration of the disk array control device according to the present invention.

FIG. 13 is a diagram showing a configuration of a channel IF unit of the disk array control device according to the present invention.

[Explanation of symbols]

1 ... Disk array controller, 11 ... Channel IF
Unit, 12: disk IF unit, 13: selector unit, 14
... Cache memory unit, 20 ... Magnetic disk device, 5
0: Host computer, 101: Microprocessor, 102: Host IF, 103: Drive IF, 1
04 CM access control unit 105 memory controller 106 memory module 110 111
Internal bus, 135... Access path 0, 136... Access path 1, 216.

Claims (6)

[Claims] A plurality of channel interfaces each having an interface with a host computer and a microprocessor for controlling input / output to and from the host computer;
A plurality of disk interface units having a microprocessor for controlling input / output to / from a disk device; a memory module for temporarily storing data stored in a disk device connected to the interface unit with the disk device; A cache memory unit having a memory controller that controls access to a memory module, the plurality of channel interface units, the plurality of disk interface units, and the plurality of channel interface units connected to the cache memory unit; A selector unit for executing an access request from the plurality of disk interface units to the cache memory unit; a microprocessor in the plurality of channel interface units and the plurality of disk interface units;
A plurality of control lines for connecting to the memory controller. 2. The method according to claim 1, wherein the memory controller receives an access request from each of the plurality of microprocessors in the plurality of channel interface units or the plurality of disk interface units via the plurality of control lines. 2. The disk array controller according to claim 1, further comprising means for performing arbitration. 3. A plurality of channel interfaces each having an interface with a host computer, a microprocessor controlling input / output with respect to the host computer, and an interface with a disk device, respectively.
A plurality of disk interface units having a microprocessor for controlling input / output to / from a disk device; a memory module for temporarily storing data stored in a disk device connected to the interface unit with the disk device; A cache memory unit having a memory controller that controls access to a memory module, the plurality of channel interface units, the plurality of disk interface units, and the plurality of channel interface units connected to the cache memory unit; A selector unit for executing an access request from the plurality of disk interface units to the cache memory unit, wherein each of the plurality of channel interface units has an access to the cache memory unit. A cache memory access control unit that controls access to the cache memory unit. Each of the plurality of disk interface units has a cache memory access control unit that controls access to the cache memory unit. The cache memory access control unit of each channel interface unit, the cache memory access control unit of each disk interface unit of the plurality of disk interface units, and a plurality of control lines connecting the memory controller. Characteristic disk array controller. 4. The memory controller receives an access request from each of the plurality of channel interface units or each cache memory access control unit in the plurality of disk interface units via the plurality of control lines, and the access request is received by the memory controller. 4. The disk array control device according to claim 3, further comprising means for performing arbitration when a conflict occurs. 5. A plurality of channel interfaces each having an interface with a host computer, a microprocessor for controlling input / output with respect to the host computer, and an interface with a disk device, respectively.
A plurality of disk interface units having a microprocessor for controlling input / output to / from a disk device; a memory module for temporarily storing data stored in a disk device connected to the interface unit with the disk device; A cache memory unit having a memory controller that controls access to a memory module, the plurality of channel interface units, the plurality of disk interface units, and the plurality of channel interface units connected to the cache memory unit; A selector unit for executing an access request from the plurality of disk interface units to the cache memory unit; a microprocessor in the plurality of channel interface units and the plurality of disk interface units;
A plurality of control lines for connecting to the selector unit. 6. The selector unit receives an access request from each of the microprocessors in the plurality of channel interface units or the plurality of disk interface units via the plurality of control lines, and when the access requests conflict with each other. 6. The disk array controller according to claim 5, further comprising means for performing arbitration.