JP4485503B2 - Disk array control device and disk array control method - Google Patents

Description

  The present invention relates to a controller for a disk array device that divides data and stores it in a plurality of magnetic disk devices.

Compared with the I / O performance of the main memory of a computer, the I / O performance of a subsystem using a magnetic disk device used as a secondary storage device is about 3 to 4 digits smaller, so that this difference has been reduced conventionally. Efforts are being made at various locations to improve subsystem I / O performance.
As one method for improving the I / O performance of the subsystem, a system called a so-called disk array, which is a means for configuring a subsystem with a plurality of magnetic disk devices and dividing the data into a plurality of magnetic disk devices. It has been known.

For example, in one prior art (hereinafter referred to as prior art 1), as shown in FIG. 2, a plurality of channel I / F units 111 that execute data transfer between the host computer 101 and the disk control device 2, and a magnetic disk device 120, a plurality of disk I / F units 112 that execute data transfer between the disk control device 2, a cache memory unit 115 that temporarily stores data of the magnetic disk device 120, data of the magnetic disk 120, and a disk control device 2, the cache memory unit 115 and the shared memory unit 114 are configured to be accessible from the all channel I / F unit 111 and the disk I / F unit 112.
In this prior art 1, the channel I / F unit 111 and the disk I / F unit 112 and the shared memory unit 114, and the channel I / F unit 111 and the disk I / F unit 112 and the cache memory unit 115 are 1: 1. It is connected.

In another prior art (hereinafter referred to as prior art 2), as shown in FIG. 3, a plurality of channel I / F units 111 for executing data transfer between the host computer 101 and the disk control device 3, and a magnetic disk device 120, a plurality of disk I / F units 112 that perform data transfer between the disk control device 3, a cache memory unit 115 that temporarily stores data of the magnetic disk device 120, data of the magnetic disk 120, and a disk control device 2 is provided. The shared memory unit 114 that stores the control information related to 2 is provided.
Each channel I / F unit 111 and disk I / F unit 112 and the shared memory unit 114 are connected by a shared bus 130, and each channel I / F 111 unit and disk I / F unit 112 and the cache memory unit 115 are connected. They are connected by a shared bus 130.

Up to now, in response to demands for higher performance of disk array systems, disk array controllers have been increased in scale and component speed, such as increased number of processors and cache capacity, application of high performance processors, internal bus width It has been supported by expanding and improving bus transfer capability.
However, in the prior art 2, it is becoming difficult for the transfer capability of the internal bus to follow the increase in scale and performance of the system.

Therefore, in order to improve the internal bus performance and obtain high memory access performance, a method of connecting the processor and the memory 1: 1 as in the prior art 1 can be considered.
According to this method, the internal bus performance increases in proportion to the number of access paths connected to the memory.
However, the number of access paths connected to the shared memory and the cache memory increases in proportion to the increase in the number of installed processors.
Therefore, it is necessary to efficiently control access between each processor and memory in order to maximize the internal bus performance.

  An object of the present invention is to provide a disk array control apparatus that solves the above-mentioned problems, uses a processor-memory access path efficiently, and has a high memory access throughput, particularly a cache memory access throughput.

In order to achieve the above object, the present invention provides:
One or more interface units with a host computer, one or more interface units with a plurality of magnetic disk devices, and a physically independent one that stores data of the magnetic disk devices and control information about the disk array control device The shared memory unit has the above, and the shared memory unit can be accessed via a selector from the interface unit with the host computer or the interface unit with the plurality of magnetic disk devices. An interface unit or a disk array control device connected between the interface unit with the plurality of magnetic disk devices and the selector, and between the selector and the shared memory unit by an access path;
The selector includes a plurality of input ports from an interface unit with the host computer or an interface unit with the plurality of magnetic disk devices;
Means for interconnecting a plurality of output ports to the shared memory unit;
Means for storing connection requests from the plurality of input ports to the output port in the order in which the connection requests arrived, arbitration between the plurality of connection requests, and arbitration for assigning connection requests from the input ports to the output ports Has means,
The arbitration unit assigns an output port to the request if the first request in the connection request stored in the arrival order is a request to an output port that is currently free, and stores the connection request stored in the arrival order. If the first request is a request for an output port currently in use, the second request is examined. If the second connection request is a request for an output port that is currently free, the request is sent. If the second connection request is a request for an output port that is currently in use, the third request is examined, and since then, at most equal to the number of currently free output ports The arbitration (assignment) of the connection request to the output port is repeated.

  The shared memory units are duplexed among the physically independent shared memory units, and simultaneous access to both of the duplexed shared memory units from the selector occurs.

The shared memory unit is physically divided into a cache memory unit that temporarily stores data of the magnetic disk device and a shared memory unit that stores control information related to the cache memory unit and the disk array control device. And
The selector connected to the cache memory unit and the selector connected to the shared memory unit are physically independent,
The access path from the interface unit with the host computer and the interface unit with the plurality of magnetic disk devices to the cache memory unit or the shared memory unit is physically independent,
At least the selector connected to the cache memory unit includes the arbitration means.

  The shared memory units are duplexed between the physically independent shared memory units, and the cache memory units are duplexed between the physically independent cache memory units, and at least the cache memory unit Simultaneous access to both of the duplicated cache memory units from the selector connected to the memory occurs, and at least the selector connected to the cache memory includes the arbitration means.

  In addition, when accessing the shared memory unit or the cache memory unit from the interface unit with the host computer or the interface unit with the plurality of magnetic disk devices, an address and a command are first transmitted continuously. The data is transmitted after the access path to the shared memory unit or the cache memory unit is established.

According to the present invention, an interface unit with a host computer, or a selector unit located between an interface unit with a plurality of magnetic disk devices and a shared memory unit, the interface unit with the host computer or a plurality of magnetic disk devices. An access request from the interface unit to the shared memory unit can be efficiently distributed to an access path to the shared memory unit.
Thereby, the data transfer throughput of the disk array controller can be improved.

Examples of the present invention will be described in detail below.
Example 1
FIG. 1 shows an embodiment of the present invention.
The disk array control apparatus 1 includes a channel I / F unit 111, a disk I / F unit 112, a selector unit 113, a shared memory unit 114, an access path 0 135, and an access path 1 136.

As shown in FIG. 13, the channel I / F unit 111 is shared by one I / F (host I / F) 51 with a host computer, one microprocessor 50, one shared memory access circuit 52, and the like. It consists of one access path I / F to the memory unit 114.
At the time of data writing, the host I / F 51 divides the data sent from the host computer 101 into packets and sends them to the shared memory access circuit 52. The shared memory access circuit 52 sends a plurality of packets sent from the host I / F 51 to the shared memory unit 114 using one access path.
When reading data, the shared memory access circuit 52 sends a plurality of packets sent from the shared memory unit 114 to the host I / F 51. The host I / F 51 collects a plurality of packets sent from the shared memory access circuit 52 into one data and sends it to the host computer 101.
The microprocessor 50 controls transmission / reception of data in the host I / F 51 and the shared memory access circuit 52.
The disk I / F unit 112 has one I / F (drive I / F) with a plurality of magnetic disk devices 120, one microprocessor, one access circuit to the shared memory unit 114, and the shared memory unit 114. It is comprised from one access path I / F. The host I / F 51 shown in FIG. 13 is replaced with a drive I / F. At the time of data writing and reading, at least the same processing as that described in the description of the channel I / F unit 111 is performed.
Here, the number shown above is only one example and is not limited to the above.

The shared memory unit 114 stores data to be recorded on the magnetic disk device 120, management information of the data, and management information such as system information.
A total of four access paths 0 135 are connected to the selector unit 113, one each from the two channel I / F units 111 and the two disk I / F units 112.
The selector unit 113 is connected with two access paths 1 136 to the two shared memory units 114, one in total.
One selector unit 113 and two channel I / F units 111 and two disk I / F units 112 connected to the selector unit 113 form a group, which is called a selector group 150.
In this embodiment, the disk array control device 1 has two selector groups 150.
Since there is the above-described number of paths among the access path between the channel I / F unit and the disk I / F unit and the selector unit and the access path between the selector unit and the shared memory unit, the selector unit 113 Of the four access paths 0: 135 from the channel I / F unit 111 and the disk I / F unit 112, only two corresponding to the number of access paths 1: 136 to the shared memory unit 114 are selected. And have the function to execute.
Here, the number is merely an example, and the number is not limited to the above.

The number of access paths connected from one selector unit 113 to the shared memory unit 114 is less than the number of access paths connected from the channel I / F unit 111 and the disk I / F unit 112 to one selector unit 113. If the number is set so that the number of selector units 113 is smaller than the total number of channel I / F units 111 and disk I / F units 112, the number of access paths connected to each shared memory unit 114 is reduced. be able to.
When the problem of the LSI pin neck of the shared memory unit and the connector neck of the package occurs, the pin pin of the LSI and the connector neck of the package can be eliminated by the above.

Next, the internal configuration of the selector unit 113 will be described.
FIG. 4 shows the configuration within the selector unit 113.
The selector unit 113 includes an I / F port 210 with the channel I / F unit 111 or the disk I / F unit 112, an I / F port 211 with the shared memory unit 114, and a selector 206 that connects the two to each other. , Buffering the data error check unit 201 when performing input / output at the I / F ports 210 and 211 and the address, command, and data sent from the channel I / F unit 111 or the disk I / F unit 112 Buffer 202, address / command (adr, cmd) analysis unit 203 for analyzing addresses and commands sent from channel I / F unit 111 or disk I / F unit 112, and shared memory unit 114 A queue management unit 204 that manages the connection request to the I / F port 211 in the order of arrival of the request, Arbitrates based on the registered connection request portion comprises an arbitration unit 205 for determining the connection right to I / F port 211 of the shared memory.

When the pin neck of the LSI of the shared memory unit and the connector neck of the package occur, as described above, the number of I / F ports 210 with the channel I / F unit 111 or the disk I / F unit 112 is larger than By reducing the number of I / F ports 211 with the shared memory unit 114, those bottlenecks can be eliminated.
In this embodiment, the number of I / F ports 210 with the channel I / F unit 111 or the disk I / F unit 112 is four, and the number of I / F ports 211 with the shared memory unit 114 is two.

FIG. 12 shows the detailed configuration of the address / command (adr, cmd) analysis unit 203, queue management unit 204, and arbitration unit 205.
The address / command (adr, cmd) analysis unit 203 has four buffers 220 corresponding to the number of I / F ports 210 with the channel I / F unit 111 or the disk I / F unit 112, and is included in the buffer. An address (adr) and a command (cmd) from each I / F port 210 are stored.
The address has a length of 4 bytes, and an output port number (port No.) is shown in the first 1 byte.
The command has a length of 4 bytes, and the type of access (read: RD, write: WR, double read: 2R, double write: 2W) is shown in the first byte.
Here, when the shared memory unit 114 is duplicated, double reading and double writing may be performed.
In such a double access, since two ports are used simultaneously, it is necessary to acquire the right to use both ports.

port No. The extraction unit 221 extracts the requested port number from the address.
In this embodiment, “00” is assigned to port 0 and “11” is assigned to port 1.
The cmd type extraction unit 222 extracts the access type from the command.
In this embodiment, “00” is assigned to RD, “01” is assigned to WR, “10” is assigned to 2R, and “11” is assigned to 2W.
In the used port determination unit 223, when the access type is not double access, the port No. Is output as it is, and in the case of double access, “01” indicating it is output.
In the queue management unit 204, the port No. output from the address / command (adr, cmd) analysis unit 203 is displayed. Are registered in the management table 224 in the order of arrival.

In the arbitration unit 205, the request port No. is transmitted from the top of the management table 224. Is extracted and stored in the buffer 227.
Then, the port No. in use stored in the buffer 226 is displayed. And the request port No. in the buffer 227. Are compared by a comparator 228.
port No. Are different, the numbers are output to the selector 206 as the selector switching signals SEL0 and SEL1, and the order changer 225 in the queue manager 204 is instructed to advance the queue order by one.
port No. Are equal, the order changing unit 225 is instructed to change the order of the queues.
The order switching method will be described in the explanation of the arbitration flow in FIG.
Here, the address, the length of the command, the address or the port No. in the command. Alternatively, the place where the cmd type is indicated, port No. Alternatively, the method of assigning bits to cmd types is merely an example, and is not limited to the above.
In addition, when the shared memory unit 114 is not duplicated, double access does not occur, so the cmd type extracting unit 222 and the use port determining unit 223 are not necessary. The output of the extraction unit 221 may be directly input to the queue management unit 204.

Next, a processing procedure in the selector unit 113 will be described.
FIG. 5 shows a processing flow in one of the I / F ports 210 with the channel I / F unit 111 or the disk I / F unit 112.
First, in step 301, the process waits until an access request (REQ ON) is received from the shared memory access circuit in the channel I / F unit 111 or the disk I / F unit 112.
When an access request is received, an address (adr) and a command (cmd) are analyzed in step 302.
In step 303, it is checked whether there is an error in the address (adr) and the command (cmd). If there is an error, error processing is performed in step 315, and the process returns to the access request waiting state in step 301.
If there is no error, in step 304, the request is registered in the queue as a connection request to the I / F port 211 with the shared memory unit 114.
Then, arbitration is performed based on the contents of the queue.
In step 305, the process waits until the requested I / F port 211 with the shared memory unit 114 can be acquired.
If acquired, the selector 206 is switched in step 306 to connect the I / F port 210 that issued the request and the acquired I / F port 211.

Next, in step 307, an access request (REQ ON) is issued to the shared memory (SM) unit 114, and an address (adr) and a command (cmd) are transmitted.
In step 308, the process waits until an access approval (ACK ON) is returned from the shared memory unit 114.
When access approval (ACK ON) is returned, in step 309, access approval (ACK ON) is returned to the channel I / F unit 111 or the shared memory access circuit in the disk I / F unit 112.
In step 310, when data is written, the data sent from the shared memory access circuit is transmitted to the shared memory unit 114.
When data is read, the data sent from the shared memory unit 114 is sent to the shared memory access circuit.

At that time, an error is checked in step 311.
If an error is found, error processing is performed in step 315, and the process returns to the access request waiting state in step 301.
If there is no error, it is checked in step 312 that the status (Status) is received, and data is transmitted until the status (Status) is received.
When the status (Status) arrives, in step 313, the shared memory unit is instructed to withdraw access approval (ACK ON), and the process returns to the access request waiting state in step 301.

Next, the arbitration method in step 304 will be described.
FIG. 6 shows an arbitration flow.
In step 401, it is checked whether there is an empty output port and waits until an empty port is created.
If there is an empty port in step 401, the head request among the connection requests stored in the queue management unit 204 in the order of arrival is checked in step 402.
If the request is for a currently available output port in step 403, an output port is assigned to the request in step 404.
In step 403, if the head request in the connection request stored in the queue management unit 204 in the order of arrival is a request to the currently used output port, the queue head request (number of free ports + 1) is obtained in step 406. ) And go back to step 401.
When the output port is assigned in step 404, the queue order is advanced by one in step 405, and the process returns to step 401.
By performing the above-described control, it is possible to efficiently allocate the I / F port 211 on the shared memory unit side, and high-throughput data transfer can be realized.

In addition, as shown in FIG. 9, the shared memory unit 114 is duplexed between the physically independent shared memory units 114 to form a duplexed area (160). That is, when two shared memory units 114 are duplicated, the same data is written in each shared memory unit. Further, the entire shared memory unit can be duplicated, or a part of each shared memory unit can be duplicated.
In the disk array control device 4 in which simultaneous access (double access) from the selector unit 113 to both of the duplicated shared memory units 114 occurs, whether the request at the head of the queue is double access in steps 402 and 403 in FIG. In the case of double access, if two requested ports are free, a port is assigned, and if not, the process proceeds to step 406.
As a result, the reliability of the data stored in the shared memory unit 114 can be improved.
In addition, when transferring data to be recorded on the magnetic disk device 120, the I / F port 211 with the shared memory unit 114 can be efficiently allocated, and high-throughput data transfer can be realized.

Example 2
As shown in FIG. 10, the configuration of the disk array control device shown in FIG. 1 includes a shared memory unit 114, a cache memory unit 115 that temporarily stores data to be recorded in the magnetic disk device 120, a cache memory unit 115, A selector unit (CM selector unit) 123 connected to the cache memory unit 115 and a selector unit (SM selector unit) connected to the shared memory unit are physically divided into the shared memory unit 114 that stores control information related to the disk array control device 5. 113 is configured to be physically independent.
Then, the access path 0 135 and the access path 1 136 from the channel I / F unit 111 and the disk I / F unit 112 to the cache memory unit 115 or the shared memory unit 114 are physically made independent, and at least the cache memory unit The selector section (CM selector section) 123 connected to 115 performs the arbitration described in the first embodiment. This is the control information related to the cache memory unit 115 and the disk array controller 5 that is stored in the shared memory unit. Since the data amount of the control information is small, the time during which the port is in use is small. This is because the port can be used, and there is no particular trouble even without arbitration.

Further, as shown in FIG. 11, the shared memory unit 114 and the cache memory unit 115 are respectively duplexed between the physically independent shared memory unit 114 and the cache memory unit 115 to form a duplex region (160). In the disk array control device 6 in which simultaneous access (double access) to at least both of the duplicated cache memory units 115 from the selector unit (CM selector unit) 123 connected to the cache memory occurs, in steps 402 and 403 of FIG. Check whether the request at the head of the queue is a double access, and if it is a double access, if the two requested ports are free, assign a port; otherwise, proceed to step 406. This is performed by the connected selector unit (CM selector unit) 123.
As a result, the reliability of the data stored in the shared memory unit 114 can be improved.
In addition, when transferring data to be recorded on the magnetic disk device 120, the I / F port 211 with the cache memory unit 115 can be efficiently allocated, and high-throughput data transfer can be realized.

Example 3
FIG. 7 illustrates the cache from the shared memory (SM) access circuit in the channel I / F unit 111 or the disk I / F unit 112 to the shared memory unit 114 or from the channel I / F unit 111 or the disk I / F unit 112. The flow of processing when data is written from the memory (CM) access circuit to the cache memory unit 115 is shown.
When writing data, an access request (REQ) is issued from the SM or CM access circuit to the selector unit 113 or 123 at step 501, and subsequently an address (ADR) and command (CMD) are sent at steps 502 and 503.
In steps 504 and 505, the selector unit 113 or 123 performs arbitration, switches the selector, and assigns a port to the shared memory unit 114 or the cache memory unit 115.
In step 506, an access request (REQ) is issued from the selector unit 113 or 123 to the shared memory unit or cache memory unit, and subsequently, in steps 507 and 508, an address (ADR) and a command (CMD) are transmitted.

In step 509, the shared memory unit 114 or the cache memory unit 115 selects a memory module to be accessed. After selection, the access approval (ACK ON) is made to the SM or CM access circuit via the selector unit 113 or 123 in step 510. )return it.
When the SM or CM access circuit receives ACK ON, it transmits data in step 511.
When the shared memory unit 114 or the cache memory unit 115 receives all the data, it performs post-processing at step 512 and returns a status (STATUS) to the SM or CM access circuit via the selector unit 113 or 123 at step 513.
Upon receiving STATUS, the selector unit 113 or 123 instructs the shared memory unit 114 or the cache memory unit 115 to withdraw access approval (ACK OFF) in step 514.
When receiving the STATUS, the SM or CM access circuit instructs the selector unit 113 or 123 to cancel the access approval (ACK OFF) in step 515.

FIG. 8 illustrates a cache memory access circuit in the channel I / F unit 111 or the disk I / F unit 112 from the shared memory unit 114 to the shared memory access circuit in the channel I / F unit 111 or the disk I / F unit 112. The flow of processing when data is read from the cache memory unit 115 is shown.
Processing steps 601 to 610 at the time of reading data are the same as processing steps 501 to 510 at the time of writing data.

Thereafter, in the shared memory unit 114 or the cache memory unit 115, pre-reading processing is performed in step 611.
In step 612, data is sent to the SM or CM access circuit via the selector unit 113 or 123.
When the data transmission is completed, the shared memory unit 114 or the cache memory unit 115 performs post-processing at step 613, and returns STATUS to the SM or CM access circuit via the selector unit 113 or 123 at step 614.
Upon receiving STATUS, the selector unit 113 or 123 instructs the shared memory unit 114 or the cache memory unit 115 to withdraw access approval (ACK OFF) in step 615.
When receiving the STATUS, the SM or CM access circuit instructs the selector unit 113 or 123 to withdraw the access approval (ACK OFF) in step 616.

  As described above, when accessing the shared memory unit 114 or the cache memory unit 115 from the channel I / F unit 111 or the disk I / F unit 112, the address and the command are first transmitted continuously and shared. By sending the data after the access path to the memory unit 114 or the cache memory unit 115 is established (step 510 or 610), the selector unit 113 or 123 does not need to buffer the transfer data, and the selector unit 113 Alternatively, the control at 123 is simplified and the access throughput to the memory can be improved.

It is a figure which shows the structure of the disk array control apparatus by this invention. It is a figure which shows the structure of the conventional disk array control apparatus. It is a figure which shows the structure of the conventional disk array control apparatus. It is a figure which shows the structure of the selector part in the disk array control apparatus by this invention. It is a figure which shows the operation | movement flow in a selector part. It is a figure which shows the operation | movement flow in the arbitration part in a selector part. It is a figure which shows a sequence when writing data in a shared memory part or a cache memory part. It is a figure which shows a sequence when reading data from a shared memory part or a cache memory part. It is a figure which shows the other structure of the disk array control apparatus by this invention. It is a figure which shows the other structure of the disk array control apparatus by this invention. It is a figure which shows the other structure of the disk array control apparatus by this invention. It is a figure which shows the detailed structure of the part of the selector part in the disk array control apparatus by this invention. It is a figure which shows the structure of a channel I / F part.

Explanation of symbols

1, 4, 5, 6 Disk array controller 50 Microprocessor 51 Host I / F
52 Shared Memory Access Circuit 101 Host Computer 111 Channel I / F Unit 112 Disk I / F Unit 113 Selector Unit (SM Selector Unit)
114 Shared memory unit 115 Cache memory unit 120 Magnetic disk unit 123 CM selector unit 135 Access path 0
136 Access path 1
150 selector group

Claims (4)

A disk array control method comprising a selector having a signal input port and a signal output port, wherein a signal including a connection request destination address is input to the signal input port,
Examining the port number to which the signal input to the signal input port is requesting connection;
Storing the port number for which the connection is requested, and managing the port number as a connection request queue;
Checking whether the port for which the connection is requested is free or occupied, and determining the number of free ports;
If the port for which the connection is requested is occupied, no port is assigned to the connection request, and the first connection request in the queue (the number of free ports + 1). ) First step,
A disk array control method comprising: allocating the port to the connection request when the port for which the connection is requested is free. In addition to the above steps,
2. The disk array control method according to claim 1, further comprising a step of registering in the queue management table the port number for which the connection is requested and the arrival order of the requested input signal. In addition to the above steps,
3. The disk array control method according to claim 1, further comprising a step of checking whether or not the input signal is a double access. Check if the port for which the connection is requested is free or occupied , and check the number of free ports .
Or two ports that are requested the connection is free, examine whether occupied, the disk array control method according to claim 3, characterized by the step of examining the number of ports available.

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