JP4452697B2 - Disk array controller - Google Patents

Description

  The present invention relates to a disk array control device that stores data in a plurality of magnetic disk devices.

  Compared with the I / O performance of a main storage of a computer using a semiconductor storage device as a storage medium, the I / O performance of a disk subsystem using a magnetic disk as a storage medium (hereinafter referred to as “subsystem”) is 3 to 4 digits. Efforts have been made to reduce this difference to a small extent and to improve the I / O performance of the subsystem. As one method for improving the I / O performance of a subsystem, a so-called disk array system is known in which a subsystem is composed of a plurality of magnetic disk devices and data is stored in the plurality of magnetic disk devices. Yes.

  FIG. 2 shows the configuration of a conventional disk array. A plurality of channel IF units 11 that execute data transfer between the host computer 50 and the disk array control device 2, and a plurality of disk IF units 12 that execute data transfer between the magnetic disk device 20 and the disk array control device 2. The cache memory unit 14 that temporarily stores data of the magnetic disk device 20 and the control information related to the disk array control device 2 (for example, the channel IF unit and the data transfer control between the disk IF unit and the cache memory unit 14) Information) and the cache memory unit 14 and the shared memory unit 15 are accessible from all channel IF units 11 and disk IF units 12. In this disk array, the channel IF unit 11, the disk IF unit 12, and the shared memory unit 15 are connected, and the channel IF unit 11, the disk IF unit 12, and the cache memory unit 14 are connected on a one-to-one basis. . Hereinafter, such a connection form is referred to as a star connection.

  The channel IF unit 11 includes an interface for connecting to the host computer 50 and a microprocessor (not shown) that controls input / output to the host computer 50. The disk IF unit 12 includes an interface for connecting to the magnetic disk device 20 and a microprocessor (not shown) that controls input / output to the magnetic disk device 20. The disk IF unit 12 also executes a RAID function.

  FIG. 3 shows another conventional disk array configuration. A plurality of channel IF units 11 that execute data transfer between the host computer 50 and the disk array control device 3, a plurality of disk IF units 12 that execute data transfer between the magnetic disk device 20 and the disk array control device 3, and a magnetic Control information related to the cache memory unit 14 that temporarily stores data of the disk device 20 and the disk array control device 3 (for example, information related to data transfer control between the channel IF unit and the disk IF unit and the cache memory unit 14) The channel IF unit 11, the disk IF unit 12, and the shared memory unit 15 are connected by a shared bus 130, and the channel IF unit 11, the disk IF unit 12, and the cache memory unit 14 are connected to each other. They are connected by a shared bus 131. Hereinafter, such a connection form is referred to as a shared bus connection form.

  To make the architecture of the disk array scalable, add a disk IF unit according to the disk capacity (number of logical volumes) connected to the disk controller, and also according to the number of necessary channels with the host computer. Therefore, it is necessary to add a channel IF unit in the disk array device. However, in the shared bus connection type disk array controller, when the channel IF unit and the disk IF unit are added, the shared bus becomes a bottleneck, and the access path between the channel IF unit and the disk IF unit and the cache memory unit, or The throughput of the access path between the channel IF unit and the disk IF unit and the shared memory unit cannot be made scalable in correspondence with the addition of the channel IF unit or the disk IF unit.

  In the shared bus connection type, when a high-performance processor is used for the microprocessor provided in the channel IF unit and the microprocessor provided in the disk IF unit, the shared bus is compared with the performance of these processors. The transfer capability becomes a bottleneck and it becomes difficult to follow the increase in processor speed.

  Furthermore, in the shared bus connection type, when a failure occurs in any channel IF unit (or disk IF unit) of a plurality of channel IF units (or a plurality of disk IF units) connected to the shared bus, It is difficult to specify the generated channel IF unit (or disk IF unit).

  On the other hand, in the star array type disk array control device, the internal path performance can be increased in proportion to the number of access paths connected to the shared memory unit or cache memory unit. Alternatively, the internal path performance can be increased according to the performance of the processor used. In addition, since the channel IF unit, the disk IF unit, and the cache memory unit and the channel IF unit, the disk IF unit, and the shared memory unit are star-connected, the failed channel IF unit (or the disk IF) It is also easy to specify the (part).

  In the star connection type disk array control device, when the number of channel IF units or disk IF units mounted in the disk array control device is increased, the channel IF unit, the disk IF unit and the cache memory unit, and the channel IF The number of access paths between the storage unit and the disk IF unit and the shared memory also increases. In addition, the use of high-speed channels such as fiber channels for the connection between the host computer and the disk array control device has led to a further increase in throughput required for the disk array control device. In order to satisfy this requirement, it is effective to increase the number of access paths between the channel IF unit, disk IF unit, and cache memory unit, and between the channel IF unit, disk IF unit, and shared memory, and improve internal path performance. It is.

  However, the data amount of one data stored in the cache memory is considerably larger than the data amount of one control information stored in the shared memory. For example, in a disk controller connected to the mainframe, one data stored in the cache memory is about several kilobytes (for example, 2 kilobytes), whereas one control stored in the shared memory is one. The information is about several bytes (for example, 4 bytes). In a disk controller connected to an open host computer, one data stored in the cache memory is about several tens of bytes (for example, 64 Kbytes), whereas one data stored in the shared memory is one. The control information is about several bytes (for example, 4 bytes). Therefore, the amount of data transferred between the channel IF unit and disk IF unit and the cache memory unit is considerably larger than the amount of data transferred between the channel IF unit and disk IF unit and the shared memory unit. The data width of the access bus between the channel IF unit, the disk IF unit, and the cache memory unit needs to be wider than the data width of the access path between the channel IF unit, the disk IF unit, and the shared memory unit. For example, the former access path is composed of a 16-bit bus, and the latter is composed of a 4-bit bus. For this reason, when the number of access paths between the channel IF unit, the disk IF unit, and the cache memory unit is increased, there arises a problem of LSI pin neck of the cache memory unit and connector neck of the package.

  On the other hand, in order to shorten the response time of the disk array controller to the host computer, it is necessary to shorten the access time to the control information stored in the shared memory unit as much as possible.

  In addition, in response to the recent trend toward open systems, a multi-platform storage subsystem is required. That is, a high-speed interface such as Fiber Channel and a low-speed ESCON (Enterprise Systems Connection; ESCON is a registered trademark of International Business Machines, Corp.) or SCSI (Small It is necessary to support a low-speed interface such as a computer system interface channel with the same disk array controller. For this reason, for example, it is necessary to install a channel IF section and disk IF section for high-throughput fiber channels and a channel IF section and disk IF section for low-throughput SCSI channels in the same disk array device and operate them simultaneously. . For this purpose, it is necessary to perform efficient access between the channel IF unit and the disk IF unit having different types of interfaces and the cache memory.

  SUMMARY OF THE INVENTION An object of the present invention is to solve the above-described problems, enable efficient use of all access paths between a channel IF unit, a disk IF unit and a cache memory, and a disk with high data transfer throughput to the cache memory. It is to provide an array controller.

In order to solve the above object, in the disk array control apparatus of the present invention, the first channel interface connected to the first computer having the interface of the first type and the bandwidth from the interface of the first type. A second channel interface connected to a second computer having an interface of a second narrow type, a second channel interface different from the first channel interface, and a first disk device connected to a first disk device having an interface of a third type. A second disk interface different from the first disk interface connected to a second disk device having a first disk interface and a fourth type interface having a narrower bandwidth than the third type interface; A first channel interface and said first A first selector connected to the disk interface via a plurality of physical first access paths, and a second selector connected to the second channel interface and the second disk interface via a plurality of physical second access paths Are connected to the first channel interface and the first disk interface through a plurality of physical third access paths through the first selector but not through the second selector, and the second channel. A cache memory connected to the interface and the second disk interface via a plurality of physical fourth access paths through the second selector but not through the first selector, and the first access path And the second access path have the same bandwidth, and the third access path Bandwidth of the than the bandwidth fourth access path is narrow, characterized in that.

In the disk array control apparatus of the present invention, the number of the third access paths connected from the first selector to the cache memory is connected from the first channel interface and the first disk interface to the first selector. The number of the fourth access paths connected to the cache memory from the second selector is less than the number of the first access paths to be transmitted from the second channel interface and the second disk interface to the second selector. It is desirable that the number be less than the number of the second access paths connected to the.

Furthermore, in the disk array control apparatus of the present invention, the first computer having the interface of the first type, the first access path connecting the first selector, and the bandwidth of the interface of the first type. A second computer having an interface that is a narrow second type, a second access path that connects a second selector, a first disk device having an interface that is a third type, and the first A third access path for connecting the selector, a second disk device having a fourth type interface having a narrower bandwidth than the third type interface, and a fourth disk unit for connecting the second selector to the second disk device. An access path, a fifth access path connecting the first selector and the cache memory, the second selector and the cache memory. And the first access path, the second access path, the third access path, and the fourth access path are equal in bandwidth, and The bandwidth of the sixth access path is narrower than the bandwidth of the five access paths.

Furthermore, in the disk array control apparatus of the present invention, the total number of access paths of the first access path and the third access path is greater than the number of the fifth access paths, and the second access path The total number of paths and the fourth access path is preferably larger than the number of the sixth access paths.

  As described above, according to the present invention, it is possible to prevent the data transfer throughput of the entire disk array device from being limited due to the bandwidth of the selector unit 13 in the disk array control device 1 and the access path connected thereto. It becomes possible. Thereby, the data transfer throughput of the disk array controller is improved.

  Embodiments of the disk array control apparatus of the present invention will be described below with reference to the drawings.

  FIG. 1 shows an embodiment of a disk array control apparatus of the present invention.

  The disk array control apparatus 1 is roughly divided into two mainframe channel IF units 411 for connecting to the mainframe 50, two FC (Fiber Channel) channel IF units 413 for connecting to the workstation 51, Two SCSI disk IF units 414 for connection to the magnetic disk 20, two FC disk IF units 415 for connection to the magnetic disk 20, four selector units 13, two cache memory units 14, and two A shared memory unit, an access path 0: 135, an access path 1: 136, and an access path 2: 137. In this embodiment, it is assumed that the bandwidths per access path 0: 135 and access path 1: 136 are all equal (for example, 200 MB / sec). Hereinafter, for convenience of explanation, the main frame 50 and the workstation 51 may be referred to as a host computer.

  The mainframe channel IF unit 411 and the FC channel IF unit 413 are connected to the two IFs (host IF) 102 for the host computer, the two microprocessors 101 for controlling input / output to the host computer, and the cache memory unit 14. And an access control unit (CM access control unit) 104 that controls access to the shared memory unit 15 and an access control unit (SM access control unit) 105 that controls access to the shared memory unit 15. Data transfer between the microprocessor 101 and the shared memory unit 15 is performed. The microprocessor 101 and the host IF 102 are connected by an internal bus 106, and the CM access control unit 104 and the SM access control unit 105 are connected to the two host IFs 102.

  The SCSI disk IF unit 414 and the FC disk IF unit 415 include two IFs (drive IFs) 103 for the magnetic disk device 20, two microprocessors 101 for controlling input / output to the magnetic disk device 20, and a cache memory. An access control unit (CM access control unit) 104 that controls access to the unit 14 and one access control unit (SM access control unit) 105 to the shared memory unit 15, and the magnetic disk device 20 and the cache memory Data transfer between the units 14 and control information between the microprocessor 101 and the shared memory unit 15 are executed. The microprocessor 101 and the drive IF 103 are connected by an internal bus 106, and the CM access control unit 104 and the SM access control unit 105 are connected to two drive IFs 103. The disk IF unit also executes the RAID function.

  The cache memory unit 14 includes a cache memory (CM) controller 105 and a memory module 106, and stores data to be recorded on the magnetic disk device 20. The shared memory unit 15 includes a shared memory (SM) controller 115 and a memory module 106, and stores control information.

  Next, the mainframe channel IF unit 411, the FC channel IF unit 413, the SCSI disk IF unit 414, the FC disk IF unit 415, the cache memory unit 14 and the shared memory, which are one of the features of the present embodiment, are described. A connection form with the memory unit 15 will be described.

  Two access paths 0: 135 are connected to each CM access control unit 104 in the mainframe channel IF unit 411, FC channel IF unit 413, SCSI disk IF unit 414, and FC disk IF unit 415, respectively. They are connected to the duplexed selector unit 13. One selector unit 13 includes one mainframe channel IF unit 411 and one FC channel IF unit 413, and a SCSI disk IF unit 414 and an FC disk IF unit 415. Access path 0: 135 is connected. In addition, two access paths 1: 136 are connected to one selector unit 13, and they are connected to the CM controller 107 in the duplicated cache memory unit 14. Therefore, a total of four access paths 1: 136 are connected to the CM controller 107 from the four selector units 13.

  The selector unit 13 receives an access request from the mainframe channel IF unit 411, the FC channel IF unit 413, the SCSI disk IF unit 414, the FC disk IF unit 415, the channel IF unit 11, or the disk IF unit 12 When there are more than two corresponding to the number of access paths 1: 136 to the memory unit 14, only two of these access requests are selected and executed.

  In order to improve the throughput of the disk array controller 1, the mainframe channel IF unit 411, the FC channel IF unit 413, the SCSI disk IF unit 414, and the FC disk IF unit 415 and the cache memory unit It is effective to increase the number of access paths and improve internal path performance. However, as the number of access paths increases, as described above, the mainframe channel IF unit 411, the FC channel IF unit 413, the SCSI disk IF unit 414, the FC disk IF unit 415, and the cache memory unit Since the data width of the access path between the access point 14 and the access point 14 needs to be wide, there arises a problem of an LSI pin neck of the cache memory unit 14 and a connector neck of the package. Therefore, in the present embodiment, the number of access paths connected from one selector unit 13 to the cache memory unit 14 is set to the mainframe channel IF unit 411, the FC channel IF unit 413, the SCSI disk IF unit 414, and Less than the number of access paths connected from the FC disk IF unit 415 to one selector unit 13, the mainframe channel IF unit 411, the FC channel IF unit 413, the SCSI disk IF unit 414, and the FC disk By making the total number of selector units 13 smaller than the total number of IF units 415, the number of access paths connected to the cache memory unit 14 is reduced.

  The selector unit 13 is duplicated, and one main frame channel IF unit 411, one FC channel IF unit 413, one SCSI disk IF unit 414, and one FC disk IF unit 415 are connected to one unit. The reason why two access routes to the cache memory unit 14 are provided is that even if a failure occurs in one access route, the cache memory unit 14 can be accessed by the other access route, thereby improving fault tolerance. Because.

  On the other hand, in order to shorten the response time of the disk array control device 1 to the host computer, it is necessary to shorten the access time to the control information stored in the shared memory unit 15 as much as possible. When the SM access control unit 105 and the SM controller 108 are connected via the selector unit as in the CM access control unit 104 and the CM controller 105 shown in FIG. 1, due to processing overhead in the selector unit. The access time to the control information stored in the shared memory unit 15 cannot be shortened. Further, as described above, the data length of one control information stored in the shared memory unit 15 is considerably smaller than the data length of one data stored in the cache memory unit 14, so that the data width of the access path 2: 137 Can be less than half the data width of the access path 0: 135. Therefore, even if the number of access paths to the shared memory unit 15 is increased, problems such as an insufficient number of pins of the LSI of the shared memory memory controller (the shared memory controller is not shown in FIG. 2) in the shared memory unit rarely occur. . Therefore, the SM access control unit 114 in the mainframe channel IF unit 411, the FC channel IF unit 413, the SCSI disk IF unit 414, and the FC disk IF unit 415, and the SM controller 115 in the shared memory unit 15. Are directly connected by an access path 2: 137.

  Next, the access from the mainframe channel IF unit 411, the FC channel IF unit 413, the SCSI disk IF unit 414, and the FC disk IF unit 415 to the cache memory unit 14 will be described.

  FIG. 4 shows a configuration within the CM access control unit 104. The CM access control unit 104 includes a selector 302, a packet buffer 303 for temporarily storing addresses, commands, and data, a path IF 301 with an access path 0: 135 connected to the selector unit 13, a data error check unit 300, and data A transfer control unit 310. The two ports of the selector 302 are connected to the host IF 102 or the drive IF 103 by the data line 210. The other two ports of the selector 302 are connected to the path IF 301. The path IF 301 is connected to the selector unit 13 with an access path 0: 135. The data transfer control unit 310 is connected to the host IF 102 or the drive IF 103 via a control line 1: 211 and is connected to the data transfer control unit 315 in the selector unit 13 via a control line 2: 212. In addition, the data transfer control unit 310 arbitrates an access request from the host IF 102 or the drive IF 103 by the arbiter 308 and switches the selector 302.

  FIG. 5 shows a configuration within the selector unit 13. The selector unit 13 includes an eight path IF 301 with an access path 0: 135 connected to the channel IF unit 11 and the disk IF unit 12 and a four path IF 301 with an access path 1: 136 connected to the CM controller 105. A selector 306, a packet buffer 303, a data error check unit 300, an address / command (adr, cmd) analysis unit 305 that analyzes the address and command sent from the CM access control unit 104, and data transfer A control unit 315 is included. The data transfer control unit 315 is connected to the data transfer control unit 310 in the CM access control unit 104 through the control line 2: 212, and is connected to the data transfer control unit 315 in the CM controller 105 through the control line 3: 213. In addition, the data transfer control unit 315 performs arbitration of access requests from the eight access paths 0: 135 analyzed by the adr / cmd analysis unit 305 by the arbiter 308 and switches the selector 306. When there is a difference in data transfer speed between the access path 0: 135 side path and the access path 1: 136 side path, the packet buffer 303 buffers part or all of the data to be transferred in order to absorb the speed difference. Ring.

  The adr / cmd analysis unit 305 includes a buffer for storing addresses and commands, an adr extraction unit, and a cmd extraction unit (not shown). The adr and cmd analysis unit 305 stores addresses and commands in buffers assigned to each of the eight access paths 0: 135 connected to the CM access control unit 104. The adr extraction unit and the cmd extraction unit determine the CM controller 105 to be accessed and the type of access, and send them to the arbiter 308 in the data transfer control unit 315.

  FIG. 6 shows a configuration in the cache memory unit 14. The cache memory unit 14 includes a CM controller 105 and a memory module 106. The CM controller 105 includes four path IFs 301 with an access path 1: 136 connected to the selector unit 13, a selector 304, a packet buffer 303 for temporarily storing data, a data error check unit 300, and a memory module 106. It has a memory control unit 307 that controls access, an adr / cmd analysis unit 305 that analyzes addresses and commands sent from the CM access control unit 104, and a data transfer control unit 315. The data transfer control unit 315 is connected to the data transfer control unit 315 in the selector unit 13 by the control line 3: 213. In addition, the data transfer control unit 315 performs arbitration of access requests from the four access paths 1: 136 analyzed by the adr / cmd analysis unit 305 by the arbiter 308 and switches the selector 304.

  The adr / cmd analysis unit 305 includes a buffer, an adr extraction unit, and a cmd extraction unit (not shown). The adr and cmd analysis unit 305 stores addresses and commands in buffers assigned to each of the four access paths 1: 136 connected to the CM controller 105. The adr extraction unit and the cmd extraction unit determine the address of the memory to be accessed and the type of access, and send them to the memory control unit 307. Also, access requests from the four access paths 1: 136 are sent to the arbiter 308 in the data transfer control unit 315.

  Next, a procedure when accessing the cache memory unit 14 will be described. When accessing the cache memory unit 14, the microprocessor 101 instructs the host IF 102 or the drive IF 103 to start access to the cache memory unit 14.

  Upon receiving the access start instruction, the host IF 102 or the drive IF 103 sends a signal indicating access start to the data transfer control unit 310 in the CM access control unit 104 through the control line 1: 211. At the same time, an address, a command, and data (only when data is written) are transmitted through the data line 210.

  The CM access control unit 104 stores the address, command, and data (only when data is written) sent through the data line 210 in the packet buffer 303. The data transfer control unit 310 performs arbitration, determines the right to use the path IF 301, and switches the selector 302.

  FIG. 7 shows a flow of access from the CM access control unit 104 to the CM controller 105 when data is written to the cache memory unit 14. When the right to use the access path 0: 135 is determined by arbitration, the data transfer control unit 310 in the CM access control unit 104 starts access to the data transfer control unit 315 in the selector unit 13 through the control line 2: 212. A signal (REQ) is output (step 501). Subsequently, an address (ADR) and a command (CMD) are transmitted (step 502).

When the data transfer control unit 315 in the selector unit 13 receives the REQ signal from the CM access control unit 104, the data transfer control unit 315 receives the next address and command sent through the access path 0: 135, and the adr and cmd analysis unit 305 Arbitration is performed based on the analyzed access request (step 503). If the connection right to the access path 1: 136 is obtained as a result of the arbitration, the data transfer control unit 315 switches the selector 306 (step 504) and controls the data transfer in the CM access control unit 104 by the control line 2: 212. A signal (ACK) indicating that the right to connect to access path 1: 136 has been obtained is returned to unit 310 (step 505). Next, the data transfer control unit 315 outputs a signal (REQ) indicating an access start to the data transfer control unit 315 in the CM controller 105 through the control line 3: 213 (step 506). Subsequently, an address and a command are transmitted (step 507).

  Upon receiving the ACK signal, the CM access control unit 104 reads data (DATA) from the packet buffer 303 and sends it to the access path 0: 135 via the selector 302 and the path IF 301. The selector unit 13 sends the data sent through the access path 0: 135 to the access path 1: 136 via the path IF 301 and the selector 306 (step 509).

  When the data transfer control unit 315 in the CM controller 105 receives the REQ signal through the control line 3: 213, the data transfer control unit 315 receives an address and a command sent next through the access path 1: 136, and the adr / cmd analysis unit 305 Arbitration is performed based on the analyzed access request (step 508), and the selector 304 is switched. Data sent through the access path 1: 136 is stored in the packet buffer 303. If the access right to the memory module 106 is obtained as a result of the arbitration, the memory control information is sent to the memory control unit 307, and preprocessing for memory access is performed (step 510). Next, data is read from the packet buffer 303 and written to the memory module 106 via the selector 304 (step 511).

  When access to the memory module 106 is completed, post-processing of memory access is performed, and the data transfer control unit 315 generates a status (STATUS) indicating an access status (step 512). Next, the status is sent to the CM access control unit 104 via the selector unit 13 (step 513). When receiving the status, the data transfer control unit 315 in the selector unit 13 turns off the REQ signal to the CM controller 105 (step 514). When receiving the status, the data transfer control unit 310 in the CM access control unit 104 turns off the REQ signal to the selector unit 13 (step 515). When the data transfer control unit 315 in the selector unit 13 confirms that the REQ signal from the CM access control unit 104 is turned off, the data transfer control unit 315 turns off the ACK signal to the CM access control unit 104 (step 516).

  Upon receiving the status, the data transfer control unit 310 in the CM access control unit 104 reports the end of access to the cache memory unit 14 to the host IF 102 or the drive IF 103 through the control line 1: 211.

  The flow of access from the CM access control unit 104 to the CM controller 105 when reading data from the cache memory unit 14 is the same as that in the case of data writing from step 501 to 508 and from step 512 onward.

  When the CM access control unit 104 receives an ACK signal in step 505, the CM access control unit 104 enters a data reception waiting state.

  When the memory access right is obtained in step 508, the CM controller 105 reads data from the memory module 106 and sends the data to the access path 1: 136 via the selector 304 and the path IF 301.

  When the selector unit 13 receives data through the access path 1: 136, it sends the data to the access path 0: 135 via the path IF 301 and the selector 306.

  When receiving data through the access path 0: 135, the CM access control unit 104 sends the data to the host IF 102 or the drive IF 103 via the selector 302 and the data line 210.

  Next, access from the mainframe channel IF unit 411, the FC channel IF unit 413, the SCSI disk IF unit 414, and the FC disk IF unit 415 to the shared memory unit 15 will be described.

  FIG. 8 shows a configuration within the SM access control unit 105. The SM access control unit 104 includes a selector 302, a packet buffer 303 for temporarily storing addresses, commands, and data, a path IF 301 with an access path 2: 137 connected to the SM controller 108, a data error check unit 300, data A transfer control unit 310 is included. Two ports of the selector 302 are connected to the microprocessor 101 by a data line 220. The other two ports of the selector 302 are connected to the path IF 301. The path IF 301 is connected to the SM controller 108 via an access path 2: 137. The data transfer control unit 310 is connected to the microprocessor 101 through a control line 5: 221, and is connected to the data transfer control unit 315 in the SM controller 108 through a control line 6: 222. In addition, the data transfer control unit 310 arbitrates an access request from the microprocessor 101 by the arbiter 308 and switches the selector 302.

  FIG. 9 shows a configuration in the shared memory unit 15. The shared memory unit 15 includes an SM controller 108 and a memory module 109. The SM controller 108 includes four path IFs 301 to the access path 2: 137 connected to the SM access control unit 105, a selector 309, a packet buffer 303 for temporarily storing data, a data error check unit 300, and a memory module 109. A memory control unit 307 that controls access to the data, an adr / cmd analysis unit 305 that analyzes addresses and commands sent from the SM access control unit 105, and a data transfer control unit 315. The data transfer control unit 315 is connected to the data transfer control unit 310 in the SM access control unit 105 by the control line 6: 222. In addition, the data transfer control unit 315 performs arbitration of access requests from the four access paths 2: 137 analyzed by the adr and cmd analysis unit 305 by the arbiter 308, and switches the selector 309.

  The adr / cmd analysis unit 305 includes a buffer, an adr extraction unit, and a cmd extraction unit (not shown). The adr and cmd analysis unit 305 stores an address and a command in a buffer assigned to each of the four access paths 2: 137 connected to the SM controller 108. The adr extraction unit and the cmd extraction unit determine the address of the memory to be accessed and the type of access, and send them to the memory control unit 307. Also, access requests from the four access paths 2: 137 are sent to the arbiter 308 in the data transfer control unit 315.

  Next, a procedure for accessing the shared memory unit 15 will be described. When accessing the shared memory unit 15, the microprocessor 101 sends a signal indicating the start of access to the data transfer control unit 310 in the SM access control unit 105 through the control line 5: 221. At the same time, an address, a command, and data (only when data is written) are transmitted through the data line 220.

  The SM access control unit 105 stores the address, command, and data (only when data is written) sent through the data line 220 in the packet buffer 303. The data transfer control unit 310 performs arbitration, determines the right to use the path IF 301, and switches the selector 302.

  FIG. 10 shows a flow of access from the SM access control unit 105 to the SM controller 108 when data is written to the shared memory unit 15. When the right to use the access path 2: 137 is determined by arbitration, the data transfer control unit 310 in the SM access control unit 105 issues a signal (REQ) indicating the start of access to the SM controller 108 via the control line 6: 222. (Step 601). Subsequently, an address, a command, and data are continuously transmitted (step 602).

  When the data transfer control unit 315 in the SM controller 108 receives the REQ signal through the control line 6: 222, the data transfer control unit 315 receives an address, a command, and data transmitted through the access path 2: 137 next. The address and command are analyzed by the adr / cmd analysis unit 305, arbitration is performed based on the access request (step 603), and the selector 309 is switched. Data is stored in the packet buffer 303. If the access right to the memory module 109 is obtained as a result of the arbitration, memory control information is sent to the memory control unit 307, and preprocessing for memory access is performed (step 604). Next, data is read from the packet buffer 303 and written to the memory module 109 via the selector 309 (step 605).

  When access to the memory module 109 is completed, post-processing of memory access is performed, and the data transfer control unit 315 generates a status (STATUS) indicating an access status (step 606). Next, the status is sent to the SM access control unit 105 (step 607). When receiving the status, the data transfer control unit 310 in the SM access control unit 105 turns off the REQ signal to the SM controller 108 (step 608).

  When the data transfer control unit 310 in the SM access control unit 105 receives the status, it reports the end of access to the shared memory unit 15 to the microprocessor 101 via the control line 5: 221.

  The flow of access from the SM access control unit 105 to the SM controller 108 when reading data from the shared memory unit 15 is the same as that in the case of data writing from step 601 to 604 and from step 606.

  After pre-processing for memory access in step 604, the SM controller 108 reads data from the memory module 109 and sends the data to the access path 2: 137 via the selector 309 and the path IF 301.

  When the SM access control unit 105 receives data through the access path 2: 137, it sends the data to the microprocessor 101 via the selector 302 and the data line 220.

  Next, other features of the present embodiment will be described.

  If the bandwidth of each selector unit 13 is different, the channel IF unit 411 for mainframe, the channel IF unit 413 for FC, the disk IF unit 414 for SCSI, or the disk IF unit 415 for FC connected to the selector unit 13 having a narrow bandwidth. Data transfer throughput of the mainframe channel IF unit 411, FC channel IF unit 413, SCSI disk IF unit 414, or FC disk IF unit 415 connected to the selector unit 13 having a wide bandwidth. There is a problem of being lowered. In such a case, between the two mainframe channel IF units 411, between the two FC channel IF units 413, between the two SCSI disk IF units 414, or between the FC disk IF unit 415 and A difference in performance occurs between the two, and the data transfer performance becomes unbalanced in the entire disk array device 1.

  Therefore, in this embodiment, the bandwidth of the selector unit 13 is made substantially equal for each selector unit 13. More specifically, the access path 0: 135 from the mainframe channel IF unit 411, the FC channel IF unit 413, the SCSI disk IF unit 414, and the FC disk IF unit 415 is assigned to any selector unit 13. Connect one by one and connect two access paths 1: 136 to the cache memory unit 14. In other words, the feature of the present embodiment is the type of channel IF unit connected to each selector unit 13 (the type of channel IF unit is the type classified by the type of interface with the host computer. 2 types of mainframe channel IF unit 411 and FC channel IF unit 413) and combinations thereof, and the type of disk IF unit (the type of disk IF unit is the type of interface with the magnetic disk device) In this embodiment, it is assumed that the combination of the number of SCSI disk IF units 414 or FC disk IF units 415 and the number of the same is used in each selector unit 13. is there. In this embodiment, it is assumed that the bandwidths per access path 0: 135 and access path 1: 136 are all equal (for example, 200 MB / sec). Thirteen bandwidths can be made equal. Also, for example, the bandwidth of the access path 0: 135 connected to the mainframe channel IF unit 411 is 100 MB / sec, and the bandwidth of the access path 0: 135 connected to the FC channel IF unit 413 is 200 MB / sec. Even when these bandwidths are made different from each other, it is possible to make the bandwidths of the selector sections 13 equal by configuring as in the present embodiment. As a result, it is possible to equalize performance between the same type of channel IF units or between the same type of disk IF units.

  According to the present embodiment, when the access frequency from each host computer is approximately the same, the access frequency to each selector unit 13 is substantially equal. In other words, the usage rate of each selector unit 13 is substantially equal. Therefore, there is a difference in throughput between the two mainframe channel IF units 411, between the two FC channel IF units 413, between the two SCSI disk IF units 414, or between the two FC disk IF units 415. It becomes difficult to occur. As a result, it is possible to balance the data transfer throughput in the entire disk array control apparatus 1, and it is possible to provide a disk array control apparatus with a high data transfer throughput. In addition to the types shown in the present embodiment, a SCSI channel, a metal channel, etc. can be considered as the type of the channel IF unit.

  Next, some modified examples of the present embodiment will be shown. In the following modification, only differences from the first embodiment will be described. In the following modified example, the description of the shared memory unit is omitted.

[Modification 1]
In the disk array control apparatus 1 shown in FIG. 11, the two selector units 13 on the left side include one main frame FC channel IF unit 410, one SCSI channel IF unit 412, and one SCSI disk IF. Are connected by a total of eight access paths 0: 135 from the unit 414 and one FC disk IF unit 415. The two selector units 13 on the right side include one SCSI channel IF unit 412, one FC channel IF unit 413, one SCSI disk IF unit 414, and one FC disk IF unit 415, respectively. Are connected by a total of eight access paths 0: 135. Furthermore, a total of four access paths 1: 1136 to the four cache memory units 14 are connected to the selector unit 13, one each.

  The selector unit 13 receives an access request from the mainframe channel IF unit 411, the FC channel IF unit 413, the SCSI disk IF unit 414, the FC disk IF unit 415, the channel IF unit 11, or the disk IF unit 12 When there are more than two corresponding to the number of access paths 1: 136 to the memory unit 14, only two of these access requests are selected and executed.

  Also in the second modification, the provision of the selector unit 13 can solve the problems of the LSI pin neck of the cache memory unit 14 and the connector neck of the package.

  Each selector unit 13 is connected to a channel IF unit and a disk IF unit connected to the fiber channel 180, and a channel IF unit and a disk IF unit connected to the SCSI channel. The type and number of connected channel IF units 11 and the type and number of disk IF units 12 are the same for each selector, and the bandwidth is uniform. As a result, as described above, the entire disk array control device 1 can balance the data transfer throughput, and a disk array control device with a high data transfer throughput can be provided.

[Modification 2]
Also in the disk array control apparatus 1 shown in FIG. 12, each selector unit 13 includes two mainframe channel IF units, one SCSI channel IF unit 412, one FC channel IF unit 413, and two SCSI channels. Disk IF unit 414 and two FC disk IF units 415 are connected. The type and number of channel IF units 11 connected to each selector unit 13 and the type and number of disk IF units 12 are the same for each selector. And have the same bandwidth.

  In the second modification, two accesses are made to the mainframe channel IF unit 411, the SCSI channel IF unit 412, the FC channel IF unit 413, the SCSI disk IF unit 414, and the FC disk IF unit 415, respectively. Paths 0: 135 are connected and connected to two different selector sections 13 one by one. By doing so, there are two access routes from one channel IF unit or disk IF unit to one cache memory unit 14. As a result, even if a failure occurs in one access path 0: 135, access path 1: 136, or the selector unit 13, the cache memory unit 14 can be accessed by another access route. Impedance can be improved.

[Modification 3]
In the disk array control apparatus 1 shown in FIG. 13, a plurality of SCSI channel IF units 412, FC channel IF units 413, SCSI disk IF units 414, FC disk IF units 415, and cache memory units 14 are connected to each other. The switches are connected by an interconnection network 140 constituted by switches (SW) 16. Also in this case, it is possible to balance the data transfer throughput of the entire disk array control apparatus 1 by equalizing the bandwidth between the SWs.

[Modification 4]
In the disk array control device 1 shown in FIG. 14, the mainframe FC channel IF unit 410, the FC channel IF unit 413, and the FC disk IF unit are connected to the host computer or the magnetic disk device through a wide bandwidth fiber channel. 415 is connected to the selector unit 13a, and the mainframe channel IF unit 411, SCSI channel IF unit 412, SCSI disk connected to the host computer or magnetic disk device via the ESCON channel 181 or the SCSI channel 182 with a narrow bandwidth. The IF unit 414 is connected to the selector unit 13b.

  In addition, eight access paths 1: 136 are connected to each selector unit 13a, two of them are connected to the four cache memory units 14, and four access paths 1: 136 are connected to each selector unit 13b. These are connected and connected one by one to the four cache memory units 14. Since the bandwidth per access path 0: 135 and access path 1: 136 is assumed to be 200 MB / sec, the bandwidth of the selector unit 13a is wider than the bandwidth of the selector unit 13b.

  As described above, a channel having a narrow bandwidth between the host computer and the selector unit to which the channel IF unit having a wide bandwidth with the host computer and the disk IF unit having a wide bandwidth with the magnetic disk device 20 are connected. The IF section and the magnetic disk apparatus are separated from the selector section to which the disk IF section having a narrow bandwidth is connected, and the bandwidth of each selector section matches the bandwidth of the channel IF section and the disk IF section connected to the selector section. By setting in this way, it is possible to balance the data transfer throughput of the entire disk array control apparatus 1. Further, it is possible to prevent the data transfer throughput from being suppressed due to the bandwidth of some selector units.

  Note that the selector unit connected to the channel IF unit and the selector unit connected to the disk IF unit may be separated.

[Modification 5]
In the disk array control device shown in FIG. 15 as well, as in the fourth modification, a selector to which a channel IF unit having a wide bandwidth with the host computer and a disk IF unit having a wide bandwidth with the magnetic disk device 20 are connected. The selector 13b and the cache connected to the channel IF section having a narrow bandwidth with the host computer and the disk IF section having a narrow bandwidth with the magnetic disk device are connected to the bandwidth between the section 13a and the cache memory section 14. The bandwidth is wider than that between the memory unit 14.

  In this modification, two access paths 0: 135 are connected to the mainframe FC channel IF unit 410, the FC channel IF unit 413, and the FC disk IF unit 415, respectively, and these are connected to two different selectors. Are connected one by one to the unit 13a, and two access paths 0: 135 are connected to the mainframe channel IF unit 411, the SCSI channel IF unit 412, and the SCSI disk IF unit 414, respectively, and they are connected in two different ways. One selector unit 13b is connected at a time. By doing so, there are two access routes from one channel IF unit or disk IF unit to one cache memory unit 14. As a result, even if a failure occurs in one access path 0: 135, access path 1: 136, or the selector unit 13, the cache memory unit 14 can be accessed by another access route. Impedance can be improved.

[Modification 6]
In the disk array control device 1 shown in FIG. 16, as in the fourth modification, a selector to which a channel IF unit having a wide bandwidth with the host computer and a disk IF unit having a wide bandwidth with the magnetic disk device 20 are connected. And a selector unit to which a channel IF unit with a narrow bandwidth between the host computer and a disk IF unit with a narrow bandwidth with the magnetic disk device are connected.

  In this modification, the bandwidth per access path 0: 135b connected to the selector unit 13b and the bandwidth per access path 1: 136b are set to the access path 0 connected to the selector unit 13a. : The bandwidth per one of 135b and the bandwidth per one of the access paths 1: 136b are narrower. For example, the bandwidth per access path 0: 135b connected to the selector unit 13a and the bandwidth per access path 1: 136b are set to 200 MB / sec (for example, the access path 2B, frequency 100 MHz), the bandwidth per access path 0: 135b connected to the selector unit 13b and the bandwidth per access path 1: 136b are, for example, 100 MB / sec (for example, the access path width is 1B and the frequency is 100 MHz, or the access path width is 2B and the frequency is 50 MHz). Therefore, the bandwidth between the selector unit 13a and the channel IF unit and the disk IF unit, and the bandwidth between the selector unit 13a and the cache memory unit 14 are the same as those between the selector unit 13b, the channel IF unit, and the disk IF unit. And the bandwidth between the selector unit 13 b and the cache memory unit 14.

  Thus, the bandwidth between the host computer and the selector unit 13a to which the channel IF unit having a wide bandwidth with the host computer and the disk IF unit having a wide bandwidth with the magnetic disk device 20 are connected is narrow. The channel IF unit and the magnetic disk device are separated from the selector unit 13b to which the disk IF unit having a narrow bandwidth is connected, and the bandwidth of each selector unit is determined as the bandwidth of the channel IF unit and the disk IF unit connected to the selector unit. Therefore, it is possible to balance the data transfer throughput of the entire disk array control device 1. Further, it is possible to prevent the data transfer throughput from being suppressed due to the bandwidth of some selector units.

[Modification 7]
Also in the disk array control apparatus shown in FIG. 17, as in the sixth modification, in this modification, the bandwidth per access path 0: 135b connected to the selector unit 13b and the access path 1: 136b are connected. The bandwidth per line is narrower than the bandwidth per access path 0: 135b connected to the selector unit 13a and the bandwidth per access path 1: 136b.

  In this modification, two access paths 0: 135 are connected to the mainframe FC channel IF unit 410, the FC channel IF unit 413, and the FC disk IF unit 415, respectively, and these are connected to two different selectors. Are connected one by one to the unit 13a, and two access paths 0: 135 are connected to the mainframe channel IF unit 411, the SCSI channel IF unit 412, and the SCSI disk IF unit 414, respectively, and they are connected in two different ways. One selector unit 13b is connected at a time. By doing so, there are two access routes from one channel IF unit or disk IF unit to one cache memory unit 14. As a result, even if a failure occurs in one access path 0: 135, access path 1: 136, or the selector unit 13, the cache memory unit 14 can be accessed by another access route. Impedance can be improved.

It is a figure which shows one Example of the disk array control apparatus of this invention. It is a figure which shows the structure of the conventional disk array control apparatus. It is a figure which shows the structure of the conventional disk array control apparatus. It is a figure which shows the structure of the CM access control part in the disk array control apparatus of this invention. It is a figure which shows the structure of the selector part in the disk array control apparatus of this invention. It is a figure which shows the structure of the cache memory part in the disk array control apparatus of this invention. It is a figure which shows the procedure at the time of the data writing to a cache memory part. It is a figure which shows the structure of the SM access control part in the disk array control apparatus of this invention. It is a figure which shows the structure of the shared memory part in the disk array control apparatus of this invention. It is a figure which shows the procedure at the time of writing of the data to a shared memory part. It is a figure which shows the other structure of the disk array control apparatus of this invention. It is a figure which shows the other structure of the disk array control apparatus of this invention. It is a figure which shows the other structure of the disk array control apparatus of this invention. It is a figure which shows the other structure of the disk array control apparatus of this invention. It is a figure which shows the other structure of the disk array control apparatus of this invention. It is a figure which shows the other structure of the disk array control apparatus of this invention. It is a figure which shows the other structure of the disk array control apparatus of this invention.

Explanation of symbols

  DESCRIPTION OF SYMBOLS 1 ... Disk array control apparatus, 411 ... Main frame channel IF part, 413 ... FC channel IF part, 414 ... SCSI disk IF part, 415 ... FC disk IF part, DESCRIPTION OF SYMBOLS 13 ... Selector part, 14 ... Cache memory part, 20 ... Magnetic disk apparatus, 50 ... Main frame, 51 ... Workstation, 101 ... Microprocessor, 102 ... Host IF 103, drive IF, 104, CM access control unit, 105, CM controller, 106, memory module, 110, 111, internal bus, 135, access path 0, 136, ..Access path 1, 137... Access path 2

Claims (4)

A first channel interface connected to a first computer having an interface of a first type;
A second channel interface different from the first channel interface connected to a second computer having a second type interface having a lower bandwidth than the first type interface;
A first disk interface connected to a first disk device having a third type of interface;
A second disk interface different from the first disk interface, connected to a second disk device having a fourth type interface with a lower bandwidth than the third type interface;
A first selector connected to the first channel interface and the first disk interface through a plurality of physical first access paths, and a plurality of physical second channels connected to the second channel interface and the second disk interface. A second selector connected by an access path;
The first channel interface and the first disk interface are connected to each other through a plurality of physical third access paths through the first selector but not through the second selector, and the second channel interface and A cache memory connected to the second disk interface via a plurality of physical fourth access paths through the second selector but not through the first selector;
With
The bandwidth of the first access path is equal to the bandwidth of the second access path;
The bandwidth of the fourth access path is narrower than the bandwidth of the third access path;
A disk array control device. The number of the third access paths connected from the first selector to the cache memory is less than the number of the first access paths connected from the first channel interface and the first disk interface to the first selector. The number of the fourth access paths connected from the second selector to the cache memory is the number of the second access paths connected from the second channel interface and the second disk interface to the second selector. The disk array control device according to claim 1, wherein the number is less. A first computer having an interface of a first type, a first access path connecting a first selector;
A second computer having an interface which is narrower second types of bandwidth from the interface is a first type, and a second access path that connects the second selector,
A third access path that connects the first disk device and said first selector having a third type in which the interface,
A fourth access path that connects the third type is a second disk device and said second selector having an interface which is fourth type narrow bandwidth from the interface,
A fifth access path connecting the first selector and the cache memory;
A sixth access path for connecting the second selector and the cache memory;
Wherein the first bandwidth of the access path and the second access path and said third access path and the fourth access path rather equal,
The bandwidth of the sixth access path is narrower than the bandwidth of the fifth access path;
A disk array control device. The total number of access paths of the first access path and the third access path is larger than the number of the fifth access paths, and the total number of the second access path and the fourth access path is The disk array control apparatus according to claim 3, wherein the number of access paths is greater than the number of the sixth access paths.

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