JP2003005916A - Disk controller and its data access method - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a disk controller having a cache memory part and a shared memory part capable of making it unnecessary to increase the number of the shared memory part, and preventing access performance form being deteriorated. SOLUTION: A data transferring path is arranged between a cache memory part and a shared memory part, and data for control which are used to be stored in the shared memory part in a conventional manner are stored through the shared memory part in the cache memory part so as to be accessed.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a disk control device, and more particularly to a cache memory unit for storing data read / written to / from a magnetic disk device, and control data for the disk control device. The present invention relates to a disk control device having two kinds of internal memories of a shared memory unit for performing the above, and even if the cache memory unit is added, it is not necessary to add the shared memory unit accordingly.

[0002]

2. Description of the Related Art In today's computer systems,
There are great expectations for improvement in processing performance, and in particular, demands for improvement in I / O performance of disk subsystems using a magnetic disk, which is a typical auxiliary storage device, as a storage medium are increasing year by year. The I / O performance of this disk subsystem (hereinafter also referred to as “subsystem”) is the I / O performance of the main memory of a computer using a semiconductor memory device as a storage medium.
Compared with the O performance, it is about 3 to 4 orders of magnitude smaller, and efforts have conventionally been made to reduce this difference, that is, to improve the I / O performance of the subsystem.

Further, in large corporations represented by banks, securities companies, telephone companies, etc., computers and storages, which were conventionally distributed in various places, are centralized in a data center to form a computer system and a storage system. It tends to reduce the cost of operating, maintaining, and managing computer and storage systems, especially for large / high-end storage systems, channel interface support for connecting to hundreds or more host computers (connectivity). ), Support for hundreds of terabytes or more of storage capacity is required.

As one method for improving the I / O performance of a subsystem, there is a so-called disk array system in which a subsystem is composed of a plurality of magnetic disk devices and data is stored in the plurality of magnetic disk devices. Are known. In the case of a disk array, a plurality of magnetic disk devices that record I / O from a host computer and a disk array control device that receives the I / O of the host computer and transfers the I / O to the plurality of magnetic disk devices (hereinafter,
It may be simply referred to as a "disk controller").

In order to improve the performance, such a disk array control device generally has a cache memory unit for storing the data read / written to / from the magnetic disk device in the control device. Is.

In addition to such a cache memory unit, there may be a shared memory unit for storing control information of the disk array controller. Such control information includes, for example, cache memory management information in the disk array control device.

The configuration of a disk array controller having such two types of internal memories, a cache memory unit and a shared memory unit, will be described below with reference to FIG.
FIG. 2 is a configuration diagram of a disk array control device in which the internal configuration according to the related art is combined with a shared bus.

The disk array controller 2 shown in FIG.
Then, the shared bus 16 allows the host IF unit 11, the disk IF unit 12, and the shared memory unit 1 which are internal components.
3. The cache memory unit 14 is connected.

The host IF section 11 executes data transfer between the host computer 50 and the disk array control apparatus 2, and the disk IF section 12 executes data transfer between the magnetic disk apparatus 5 and the disk array control apparatus 2. It is the part to do.

Further, as described above, the cache memory unit 14 is a memory for temporarily storing the data of the magnetic disk device 20, and the shared memory unit 13 stores the control information regarding the disk array controller 2. It is a memory.

Then, one disk array controller 2
Inside, shared memory unit 13 and cache memory unit 1
Reference numeral 4 denotes all host IF units 11 and disk IF units 1.
It is accessible from 2.

The host IF unit 11 also has an interface for connecting to the host computer 50 and a microprocessor (not shown) for controlling input / output to / from the host computer 50. Similarly, the disk IF unit 12 has an interface for connecting to the magnetic disk device 5 and a microprocessor (not shown) for controlling input / output to / from the magnetic disk device 5. The disk IF unit 12 also executes the RAID function.

Each IF unit is connected through a mutual coupling network using switches instead of the shared bus 16 shown in FIG.

[0014]

In the above-mentioned disk array control device, two types of internal memories are selectively used depending on the type of data to improve the performance.

By the way, the I / O throughput performance of the disk array device is greatly increased, and in order to cope with this, it is necessary to improve the processing performance of each IF unit. In the disk array control device according to this conventional technique, the utilization rate of the shared bus 16 becomes saturated as the processing performance is improved.
Due to that, throughput performance was limited. Therefore, efforts have been made to increase the throughput of the shared bus, but it is difficult to improve the bus width, driving frequency, etc. due to the configuration of the device, and there is a limit to throughput improvement.

On the other hand, cache memory has recently been
As the disk capacity increases, so does the memory capacity. As the number of disk devices is increased, the user may have to add more memory modules in the cache memory unit.

However, the shared memory unit needs to increase the memory capacity of the shared memory unit by adding the cache memory in order to store the management information for exclusive control of the cache memory access.

Therefore, in the case of the disk array control device according to the above-mentioned conventional technique, the shared memory part and the cache memory part are separated, but according to the peak capacity of the cache memory (maximum value that may be used). Then, the maximum capacity required for the shared memory is installed in advance, or otherwise, it becomes necessary to prompt the user to add the shared memory when the cache memory is added. Therefore, there is a problem that a cost is burdened to the user.

Therefore, as a solution, it is conceivable to use a part of the cache memory to store the control information of the disk array control device to be stored in the shared memory. This is because the amount of additional shared memory is usually much smaller than the amount of additional cache memory.

However, since the control information of the disk array control device to be stored in the shared memory is data that is short and frequently accessed, if a part of it is placed in the cache memory and accessed, the protocol There is a problem that access performance is expected to deteriorate due to the influence of overhead.

The present invention has been made in order to solve the above-mentioned problems of the prior art, and an object of the present invention is to provide a disk control device having two types of memories, a cache memory unit and a shared memory unit. It is an object of the present invention to provide a disk control device that does not require the addition of a shared memory unit according to the number of additions and does not deteriorate access performance.

[0022]

A transfer path is provided between a cache memory unit and a shared memory unit. Then, the control data of the disk controller is transferred using the connection network of the shared memory unit as before, and is exclusively used for the cache memory unit through the newly provided transfer path between the cache memory unit and the shared memory unit. Transfer data to the buffer. The cache memory unit access right is arbitrated between the conventional cache access and the access via the transfer path of the cache memory unit and the shared memory unit to write to the memory. This makes it possible to store some shared memory data in the cache memory without changing the protocol performance.

In this way, since the access is performed through the connection of the shared memory, even the data stored in the cache memory can be accessed without degrading the performance due to the overhead of the protocol of the cache memory data. Is possible. Also, by devising the control of the memory controller, it is possible to store the data from the shared memory part in the memory in the gap of the writing time of the data from the cache memory data path to the memory, thus improving the efficiency of the memory path. Is possible.

[0024]

BEST MODE FOR CARRYING OUT THE INVENTION An embodiment of the present invention will be described below with reference to FIGS. 1 and 3 to 13.

[Connection Network of Shared Memory and Cache Memory] First, the connection network of shared memory and cache memory will be described with reference to FIGS. 3 and 4. 3 and 4 are disks of another type in which each IF unit is connected through a mutual connection network using switches instead of the shared bus 16 shown in FIG. 2 as a connection network of shared memory and cache memory. It is a block diagram of an array control device.

Here, in the example shown in FIG. 3, both the shared network of the shared memory and the cache memory are connected networks using switches, and in the example shown in FIG. 4, only the connected network of the cache memory is switched. It is a connection network using.

In the disk array controller 2B of FIG. 3,
Shared memory unit 13, host IF unit 11, disk IF
The cache memory unit 14 and the host IF unit 11 and the disk IF unit 12 are connected to each other through a mutual connection network 21 and a mutual connection network 22 each of which includes a crossbar switch. There is.

According to this method, the throughput of the individual interconnected paths is a fraction of the shared bus, but since there are multiple paths between the two interconnected points, the load is distributed and the throughput is increased. Can be improved.

Further, a disk array controller shown in FIG. 4 in which the connection network of the shared memory and the cache memory is of a different type is also conceivable.

In this configuration, the cache memory unit 14
Between the host IF unit 11 and the disk IF unit 12,
Similar to FIG. 3, the mutual connection network 22 includes crossbar switches, but the shared memory unit 13 includes the host IF unit 1
1 and the disk IF unit 12 are directly connected.

In this way, in FIG. 4, the shared memory connection network 21 and the cache memory connection network 22 are distinguished and made independent because of the type of data handled by both. That is, the cache memory unit 14 is
Since it is a memory that temporarily stores the data read from the disk while storing it in the host, there are many sequential accesses such as packet data transfer with a long data length, and throughput performance is important for this access.

On the other hand, since the shared memory unit 13 is a memory for storing control information of the apparatus, the memory access with a lot of random accesses increases, and the response is emphasized. This is because the characteristics of these two accesses are contradictory, and if they are transferred using the same route and protocol, the performance of either will be degraded.

In the apparatus of FIG. 4, unlike FIG. 3, the shared memory coupling network 21 of the shared memory unit 13 is a direct coupling that does not use a CSW (crossbar switch) unit.
Therefore, it is convenient to shorten the response time. On the contrary, the cache memory connection network 22 of the cache memory unit 14 has a large structure, but has a hierarchical structure by a CSW (Crossbar Switch) unit in order to make multiple accesses and increase the used band.

[Structure of Disk Controller] Next, the structure of the disk controller according to the present invention will be described with reference to FIG. FIG. 1 is a block diagram of a disk control device according to the present invention.

The disk controller 1 of the present embodiment has a host IF section 11 for interfacing with the host computer 50 and a disk IF section 12 for interfacing with the magnetic disk apparatus 20. Usually, a plurality of these interfaces are often provided in order to improve the performance by parallel processing. In Figure 1,
Two are shown in each case. In addition, the disk control device 1 includes a cache memory unit 14 having different uses.
And a shared memory unit 15, which are two types of memories, and are respectively connected to the host IF unit 11 and the disk IF unit 12. Hereinafter, the cache memory is referred to as "C
The shared memory may be referred to as “M” and the shared memory may be referred to as “SM”.

The host IF section 11 has a host IF 3, a microprocessor 6, a CM access control section 4a, and an SM access control section 5a. The host IF 3 is a part in charge of an interface with the host computer 50. The microprocessor 6 is the host computer 5
This is a part for controlling input / output to / from 0. The CM access control unit 4a is a unit that controls access to the cache memory unit 14. The SM access control unit 5a is a unit that controls access to the shared memory unit 15.

Under the control of the microprocessor 6, the host IF unit 11 executes data transfer between the host computer 50 and the cache memory unit 14. As shown in FIG. 1, the microprocessor 6 and the host IF 3 are
Connected by an internal bus, the CM access control unit 4 also
It is connected to the host IF3.

Similarly, the SM access control section 5a transfers data using the SM path 40 connected to the shared memory section 15 under the control of the microprocessor 6.

The disk IF section 12 includes a drive IF2,
Microprocessor 6, CM access control unit 4b, SM
It has an access control unit 5a.

The drive IF2 is the magnetic disk device 20.
This is the part in charge of the interface with. The microprocessor 6 is a part that controls input / output to / from the magnetic disk device 20. The CM access control unit 4b is a unit that controls access to the cache memory unit 14. The SM access control unit 5b is a unit that controls access to the shared memory unit 15.

The disk IF unit 12 executes data transfer between the magnetic disk device 20 and the cache memory unit 14 under the control of the microprocessor 6. As shown in FIG. 1, the microprocessor 6 and the drive IF 2
Are connected by an internal bus, and CM access control unit 4b
Are connected to the drive IF2. Further, the disk IF unit also executes arithmetic functions such as RAID control.

Similarly, the SM access control section 5 also transfers data using the SM path 40 connected to the shared memory section 15 under the control of the microprocessor 6.

The cache memory unit 14 is a memory provided for temporarily storing data to be read from and written to the magnetic disk device 20 and accessing it to improve access performance. A plurality of cache memory units 14 are installed with the CM controller 7 and the memory module 9 as one unit according to the demand for the capacity and performance of the magnetic disk 20.

Host IF section 11 and disk IF section 12
Is connected to the crossbar switch unit 13 by the CM path 0 (31), and the cache memory unit 14 is
They are connected by CM path 1 (32).

That is, the CM path 0 (31) is connected to the CM access control section 4a of the host IF section 11 and the CM access control section 4b of the disk IF section 12, and the CM controller section 7 of the cache memory section 14 is connected. Is CM
Path 1 (32) is connected. And multiple CMs
The respective CM paths 0 (31) connected to the access control units 4a and 4b and the respective CM paths 1 (32) connected to the plurality of CM controller units 7 pass through the crossbar switch (CSW) unit 13, They are connected hierarchically.

The shared memory section 15 is a memory for storing the control data of the disk control device 1. In particular, the shared memory unit 15 stores, as control data, management information necessary for exclusive control of access to the cache memory unit 7. A plurality of shared memory units 15 are also installed with the SM controller 7 and the memory module 9 as one unit in accordance with the demand for performance.

Further, the shared memory unit 15 has the SM path 40
Thus, the host IF section 11 and the disk IF section 12 are connected.

That is, the SM access control unit 5a of the host IF unit 11 and the SM access control unit 5b of the disk IF unit 12 are shared by the shared memory unit 15 via the SM path 40.
It is connected to the SM controller unit 8 of.

Unlike the CM path, the hierarchical structure by the crossbar switch is not taken. Unlike the cache memory data, the shared memory data has a small capacity, many transactional accesses are made, and the response time is short. Since it is essential for improving performance, it also has the effect of reducing protocol overhead time due to switching. That is, the reason for having a path in which the cache memory unit and the shared memory unit are separated is because it takes into consideration that the properties of data access are different.

Also, the SM controller 8 of the shared memory unit 15 and the CM controller 8 of the cache memory unit 14
Are connected by their own CM / SM transfer path 41,
The control data stored in the shared memory unit 15 in the past can be stored in the cache memory unit 14 via the CM / SM transfer path 41.

This connection form may be a form in which the shared memory unit 15 and the cache memory unit 14 are connected in a one-to-one manner, or a plurality of cache memory units 14 are connected to one shared memory unit 15. It is also possible to connect to many points.

[Detailed Configuration of Each Part of Each Disk Controller]
Next, a more detailed configuration of each part of the disk control device according to the present invention will be described with reference to FIGS. (I) CM Access Control Unit First, the configuration of the CM access control units 4a and 4b will be described with reference to FIG. FIG. 5 shows the CM access control unit 4.
It is a block diagram of a, 4b.

The CM access control unit 4 has a selector 102.
, A packet buffer 103 for temporarily storing addresses, commands, and data, a path IF 101 for a CM path 0 (31) connected to the crossbar switch unit 13, a data error check circuit unit 100, and a data transfer control unit. 110 and.

The two ports of the selector 102 are connected to the host IF3 or the drive IF2 by the data line 29.

The other two ports of the selector 102 are connected to the path IF 101 via the packet buffer 103, and the path IF 101 is connected to the crossbar switch unit 13 by the CM path 0 (31). The data transfer control unit 110 is connected to the data transfer control unit 132 in the crossbar switch unit 13 (shown in FIG. 7 later) by the control line 2 (33). The data transfer control unit 110
Host IF3 or drive I by arbiter 108
Arbitration of access request from F2
Then, the selector 102 is switched. (II) SM Access Control Unit Next, the configuration of the SM access control units 5a and 5b will be described with reference to FIG. FIG. 6 shows the SM access control unit 5.
It is a block diagram of a, 5b.

The SM access control unit 4 uses the selector 112.
A packet buffer 113 for temporarily storing addresses, commands, and data, a path IF 111 for the SM path 0 (31) connected to the crossbar switch unit 13, a data error check circuit unit 114, and a data transfer control unit. 115 and.

The two ports of the selector 102 are connected to the host IF3 or the drive IF2 by the data line 28.

The other two ports of the selector 102 are connected to the path IF 101 via the packet buffer 113, and the path IF 101 is directly connected to the shared memory section 15 by the SM path 40. The data transfer control unit 115 uses the control line 2 (36) to share the shared memory unit 15.
It is connected to the internal data transfer control unit 152 (shown in FIG. 9 later). The data transfer control unit 115 uses the arbiter 11
The access request from the host IF 3 or the drive IF 2 is arbitrated by the switch 8 to switch to the selector 112. (III) Crossbar Switch Unit Next, the internal structure of the crossbar switch unit 13 will be described with reference to FIG. FIG. 7 is a configuration diagram of the crossbar switch unit 13.

Crossbar switch (CSW) unit 13
From the selector 136, the packet buffer 133, the path IF 131, the data error check circuit unit 130, and the CM access control unit 4, which connect the CM path 0 (31) and the CM path 1 (32) to each other. It has an address / command analysis unit 135 that analyzes the sent address and command, and a data transfer control unit 132.

The CM path 0 (31) is connected to the host IF unit 1
1. The CM path 1 (32) is connected to the disk IF unit 12, and is connected to the CM controller 7 in the cache memory unit 14.

The data transfer controller 132 controls the control line 2 (3
3) is connected to the data transfer unit 110 in the CM access control unit 4 shown in FIG. 5, and the control line 3 (34) is used to connect the data transfer control unit 148 in the CM controller 7 in the cache memory unit 14 ( (Shown in FIG. 7 below). In addition, the data transfer control unit 132 uses the arbiter 138.
C analyzed by the address / command analysis unit 135 by
The access request from the M path 0 (31) is arbitrated (arbitrated) and the selector 136 is switched.

The packet buffer 133 has CM path 0
If there is a difference in data transfer speed between the path on the (31) side and the path on the CM path 1 (32) side, in order to absorb the speed difference,
Buffer some or all of the data to be transferred.

The address / command analysis section 135 has a buffer for storing addresses and commands, an address extraction section, and a command extraction section (not shown). The address / command analysis unit 135 stores the address and the command in the buffers allocated to each of the CM paths 0 (31) connected to the CM access control unit 4. The address extracting unit and the command extracting unit determine the CM controller 7 to be accessed and send it to the arbiter 138 in the data transfer control unit 132. (IV) Cache Memory Unit Next, the internal structure of the cache memory unit 14 will be described with reference to FIG. FIG. 8 is a configuration diagram of the cache memory unit 14.

The cache memory unit 14 has a CM controller 7 and a memory module 9.

The CM controller 7 uses the path IF 141
A selector 144, a packet buffer 143 for temporarily storing data, and a data error check circuit unit 14
0, a memory control unit 147 that controls access to the memory module 9, an address / command analysis unit 145 that analyzes the address and command sent from the CM access control unit 4, and a data transfer control unit 148. .

The CM controller 7 is a CM
The data transfer control unit 148 connected to the crossbar switch unit 13 by the path 1 (32) is connected to the arbiter 18
0, the access request from the CM path 1 (32) analyzed by the address / command analysis unit 145 and the SM / CM path 41 connected to the SM controller 8 (shown in FIG. 9 later), which is a feature of the present invention. Arbitration with the access request is performed, and the selector 144 is switched.

The address / command analysis section 145 has a buffer, an address extraction section, and a command extraction section (not shown). In the address / command analysis unit 145, the CM path 1 (3
In the buffer allocated to each of 2),
Stores address and command. The address extractor and the command extractor determine the address of the memory to be accessed and the type of access, and send it to the memory controller 147. Further, the access request from the CM path 1 (32) is sent to the arbiter 148 in the data transfer control unit 148. (V) Shared Memory Unit Next, the configuration in the shared memory unit 15 will be described with reference to FIG. FIG. 9 is a configuration diagram of the shared memory unit 15.

The shared memory unit 15 includes the SM controller 8
And a memory module 9.

The SM controller 8 uses the path IF 151.
A selector 156, a packet buffer 153 for temporarily storing data, and a data error check circuit unit 15
0, a memory controller 157 that controls access to the memory module 9, an address / command analyzer 155 that analyzes the address and command sent from the SM access controller 4, and a data transfer controller 152. .

The SM controller 8 is an SM
The SM access control unit 5 directly through the path 40
The data transfer control unit 152 connected to a and 5b uses the arbiter 158 to analyze the SM path 40 analyzed by the address / command analysis unit 155.
Arbitration of access requests from the CM controller shown in FIG. 8 by switching the selector 154, that is, connecting to the memory module 9 as shown in FIG. 10 or via the path IF 151. 7 to be connected to the SM / CM path 41 is selected.

The address / command analysis section 155 has a buffer, an address extraction section, and a command extraction section (not shown). The address / command analysis unit 155 stores the addresses and commands in the buffers that are assigned to the SM paths 40 connected to the SM controller 7. The address extraction unit and the command extraction unit determine the address of the memory to be accessed and the type of access, and send it to the memory control unit 157. Also, the access request from the SM path 40 is sent to the arbiter 158 in the data transfer control unit 152.

[Memory Access Operation] Next, the memory access operation of the disk controller according to the present invention will be described in detail with reference to FIGS. 10 to 13. (I) Access to the cache memory unit First, the access procedure of the cache memory unit 14 will be described. When accessing the cache memory unit 14, the microprocessor 6 instructs the host IF 3 or the drive IF 2 to start access to the cache memory unit 14.

Host IF3 that received the instruction to start access
Alternatively, the drive IF2 is controlled by the control line 1 (30).
A signal indicating the start of access is sent to the data transfer control unit 110 in the CM access control units 4a and 4b shown in FIG. 5, and at the same time, the address, command, and data are sent through the data line 29.

The CM access control section 4 stores the address, command and data sent through the data line 29 in the packet buffer 103. Data transfer control unit 11
0 performs arbitration, determines the right to use the path IF 101, and switches the selector 102. (I-1) Cache Write Access Here, the procedure for writing data to the cache memory unit 14 will be described with reference to FIG. Figure 10
C when writing data to the cache memory unit 14
FIG. 6 is a sequence diagram showing a flow of access from the M access control units 4a and 4b to the CM controller 7.

The CM access control unit 4a shown in FIG.
When the right to use the CM path 0 (31) is determined by arbitration, the data transfer unit 110 in 4b sends the crossbar switch unit 13 through the control line 2 (33).
A signal (REQ) indicating the start of access is output to the data transfer control unit 1 (32) therein (sequence 501). Then, the address and command are transmitted (sequence 502).

Crossbar switch unit 1 shown in FIG.
The data transfer control unit 132 in 3 receives the REQ signal from the CM access control unit 4, and then the CM path 0 (3
The address and command sent through 1) are received, and arbitration is performed based on the access request analyzed by the address / command analysis unit 135 (sequence 503). When the connection right to the CM path 1 (32) is obtained as a result of the arbitration, the data transfer control unit 1
32 switches the selector 136 (sequence 50
4). Then, a signal (AC indicating that the connection to the CM path 1 (32) has been obtained to the data transfer control unit 110 in the CM access control units 4a and 4b by the control line 2 (33).
K) is returned (sequence 505).

Next, the data transfer control unit 132 in the crossbar switch unit 13 is controlled by the control line 3 (32).
A signal (REQ) indicating the start of access to the data transfer control unit 148 in the CM controller 7 shown in FIG. 8 is issued (sequence 506). Then, the address and the command are transmitted (sequence 507).

The CM access control units 4a and 4b receive the ACK
When the signal is received, the data is read from the packet buffer 103 and the data is transferred to the C via the selector 102 and the path IF 101.
Send to M path 0 (31). The crossbar switch unit 13 sends the data sent through the CM path 0 (31) to the C path via the path IF 131 and the selector 136.
It is sent to the M path 1 (32) (sequence 509).

When the data transfer control unit 148 in the CM controller 7 receives the REQ signal through the control line 3 (34), it next receives the address and command sent through the CM path 1 (32), / Arbitration is performed based on the access request analyzed by the command analysis unit 145 (sequence 508), and the selector 144 is switched. The data sent through the CM path 1 (32) is stored in the packet buffer 143.

Then, as a result of the arbitration, when the access right to the memory module 9 is obtained, the control information of the memory is sent to the memory control unit 147, and the preprocessing for the memory access is performed (sequence 510). Next, the data is read from the packet buffer 143,
It is written in the memory module 9 via the selector 304 (sequence 511).

When the access to the memory module 9 is completed, the CM controller 7 performs post-processing for memory access, and the data transfer control unit 148 displays status information (STAT) indicating the access result (access status).
US) is generated (sequence 512). Next, the status information is sent to the CM access unit 4 via the crossbar switch unit 13 (sequence 513). Upon receiving the status information (STATUS), the data transfer control unit 148 in the crossbar switch unit 13 turns off the REQ signal to the CM controller 107 (sequence 5).
14).

Then, the data transfer control unit 110 in the CM access control unit 4 turns off the REQ signal to the crossbar switch unit 13 which receives STATUS (sequence 515). The data transfer control unit 132 in the crossbar switch unit 13 uses the R from the CM access control unit 4.
When it is confirmed that the EQ signal is off, the ACK signal to the CM access control unit 4 is turned off (sequence 516). Upon receiving the status, the data transfer control unit 110 in the CM access control unit 4 uses the control line 1 (30) to send the host IF.
11 or drive IF 12 to cache memory unit 1
Report the end of access to 4. (I-2) Cache Read Access Next, a procedure for reading data from the cache memory unit 14 will be described.

When reading data from the cache memory unit 14 (read operation), the CM access control unit 4 to C
The sequence of access to the M controller 7 is sequence 50.
The sequence is the same as that from 1 to 508, and the sequence 512 and thereafter is the same as the case of writing data (write operation). Here, the CM access control unit 4 uses the sequence 506.
When it receives the ACK signal at, it enters a data reception waiting state.

The CM controller 7 executes the sequence 508.
When the memory access right is obtained at, the data is read from the memory module 9, and the data is sent to the CM path 1 (32) via the selector 144 and the path IF 141. Upon receiving the data through the CM path 1 (32), the crossbar switch unit 13 outputs the data to the CM path 0 (31), and C
The M access control units 4a and 4b are connected to the host IF3 or the drive IF2 via the selector 102 and the data line 29.
Send data to. (II) Access to Shared Memory Unit Next, an access procedure for the shared memory unit 15 will be described.

When accessing the shared memory section 15,
The microprocessor 6 instructs the host IF 3 or the drive IF 2 to start access to the shared memory unit 15.

Host IF3 that received the instruction to start access
Alternatively, the drive IF2 is controlled by the control line 1 (35).
A signal indicating the start of access is sent to the data transfer control unit 115 in the SM access control units 5a and 5b shown in FIG. 6, and at the same time, the address, command, and data are sent through the data line 28.

The SM access control units 5a and 5b store the address, command and data sent through the data line 28 in the packet buffer 113. The data transfer control unit 115 performs arbitration, determines the right to use the path IF 111, and switches the selector 112. (II-1) Shared Memory Write Access First, the procedure for writing data to the shared memory unit 15 will be described with reference to FIG. FIG. 11 is a sequence diagram showing a flow of access from the SM access control units 5a and 5b to the SM controller 8 when writing data to the shared memory unit 15.

The SM access controller 5a shown in FIG.
When the right to use the SM path 40 is determined by arbitration, the data transfer unit 115 in 5b controls the control line 2
By (36), a signal (RE indicating the start of access to the data transfer control unit 115 in the SM access control units 5a and 5b)
Q) is output (sequence 601). Then, the address and command are transmitted (sequence 602). The data transfer control unit 152 in the SM controller 8 of the shared memory unit 15 shown in FIG. 9 includes the SM access control units 5a and 5b.
From the SM path 40, the address and command sent from the SM path 40 are received, and arbitration is performed based on the access request analyzed by the address / command analysis unit 155 (sequence 6).
03). When the connection right is obtained as a result of the arbitration, the data transfer control unit 152 switches the selector 156 (sequence 504).

When the data transfer control unit 152 in the SM controller 8 receives the REQ signal through the control line 2 (35), the data transfer control unit 152 next receives the address and command sent through the SM path 140, and the address / command analysis unit. Arbitration is performed based on the access request analyzed in 155 (sequence 608), and the selector 1
Switch 56. The data sent via the SM path 40 is stored in the packet buffer 153.

When the access right to the memory module 9 is obtained as a result of the arbitration, the data transfer control unit 152 sends the control information of the memory to the memory control unit 157, and performs the preprocessing for the memory access ( Sequence 610). Next, the data is read from the packet buffer 153 and written in the memory module 9 via the selector 156 (sequence 611).

When the access to the memory module 9 is completed, the SM controller 8 performs post-processing of the memory access, and the data transfer control unit 152 performs status information (STAT) indicating the access result (access status).
US) is generated (sequence 612). Next, the status information is sent to the SM access control units 5a and 5b (sequence 613). The data transfer control unit 115 in the SM access control units 5a and 5b uses the status information (STAT
When receiving (US), the REQ signal to the SM controller 8 is turned off (sequence 614). Control line 1 (3
According to 5), the end of access to the shared memory unit 15 is reported to the host IF 3 or the drive IF 2. (II-2) Shared Memory Read Access Next, a procedure for reading data from the shared memory unit 15 will be described.

When reading data from the shared memory unit 15 (read operation), the flow of access from the SM access control units 5a and 5b to the SM controller 8 is sequence 6
The sequence is the same as the sequence from 01 to the sequence 608, and after the sequence 612, in the case of writing data (write operation)
Is the same as.

When the memory access right is obtained in sequence 608, the SM controller 8 reads the data from the memory module 9 and sends the data to the SM path 40 via the selector 156 and the path IF 151. The SM access control units 5a and 5b send data to the host IF3 or the drive IF2 via the selector 112 and the data line 28. (III) SM data / CM access As described above, the feature of the present invention is that the SM / CM path 41 is provided between the cache memory unit 14 and the shared memory unit 15, and is stored in the shared memory unit 15 in the conventional case. That is, the control data that has been stored can be stored in the cache memory unit 14 through this path.

The conditions for performing such transfer are:
When the data to be stored in the cache memory unit is determined in advance (for example, the management information from one address of the cache memory to the management information of a certain address is determined to be stored in the cache memory), the data can be stored in the shared memory unit 15. There are two possible cases when it disappears.

In the following, referring to FIGS. 12 and 13,
A procedure for transferring data from the SM control unit to the CM control unit by the SM / CM path 41 will be described. FIG. 12 is a sequence diagram showing a procedure for transferring data from the SM control unit to the CM control unit by using the SM / CM path 41.
FIG. 13 is a flowchart showing an outline of the operation of the CM controller 7 of the cache memory unit 14.

The flow of access from the SM access control units 5a and 5b to the SM controller 8 of the shared memory unit 15 when transferring data from the shared memory unit 15 to the cache memory (write operation) is shown in FIG. This is the same as the sequence 601 to the sequence 604.

In sequence 602, the SM controller 8 receives the address / command, and further stores the data sent through the SM / CM path 1 (41) in the SM buffer 143 (sequence 704). When the SM controller 8 receives all the data and completes the transmission of the data to the CM controller 9 through the SM / CM path, the data transfer control unit 152 outputs status information (STATUS) indicating the access result (access status).
Is generated (sequence 605). Then, the status information is then sent to the SM access control units 5a and 5b (sequence 613).

In this case, the SM controller 8 uses the CM
Note that the process proceeds without waiting for a response from the controller 7.

When the data transfer control unit 115 in the SM access control units 5a and 5b receives the status information (STATUS), it turns off the REQ signal to the SM controller 8 (sequence 614). And control line 1 (35)
Thus, the end of access to the shared memory unit 15 is reported to the host IF 3 or the drive IF 2.

On the other hand, in the CM controller 9, after receiving the data in sequence 704, the data address /
Arbitration is performed based on the access request analyzed by the command analysis unit 155 (sequence 70).
5) When the access right to the memory module 9 is obtained, the selector 156 is switched to the connection to the SM / CM 41 (sequence 706). Then, the CM controller 9 sends memory control information to the memory control unit 147, performs preprocessing for memory access, reads data from the packet buffer 143, and selects the selector 304.
To the memory module 9 via the (sequence 7
07), the access to the memory module 9 is completed.

The outline of the operation of the CM controller 7 of the cache memory unit 14 during this period is shown in FIG.

The address / command analysis unit 145 of the CM controller 7 analyzes whether REQ is ON (S801, S802).

When REQ is ON, arbitration is performed by the arbiter 180 of the data transfer control unit 148 (S805).

When REQ is not ON, S
SM buffer 149 connected to M / CM path 41
Whether or not the data has arrived, the address / command analysis unit 145 analyzes the command, and the arbiter 180 of the data transfer control unit 148 performs arbitration (S805).

As a result, when the output port of the CM path can be acquired (S806), the selector is switched and the CM path 1 (32) and the memory module 9 are connected according to the result of the address / command analysis (S807). Then, the data is written to or read from the memory module 9 (S808).

Then, the STATUS information is received or transmitted (S809), and finally REQOFF is received and the processing is terminated (S810).

When the output port of the SM path can be acquired (S811), the selector is switched to change the address / address.
According to the command analysis result, the SM / CM path 41 and the memory module 9 are connected (S812). Then, the data is written to or read from the memory module 9 (S813).

When neither output port can be acquired, arbitration is repeated until the output port can be acquired.

[0109]

According to the present invention, in a disk controller having two types of memories, a cache memory unit and a shared memory unit, it is not necessary to add the shared memory unit in response to the addition of the cache memory unit, and Thus, it is possible to provide a disk control device that does not deteriorate access performance.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a disk control device according to the present invention.

FIG. 2 is a configuration diagram of a disk array control device in which an internal configuration according to a conventional technique is coupled to a shared bus.

[FIG. 3] As a connection network of a shared memory and a cache memory, each IF is connected via a mutual connection network using switches for both.
It is a block diagram of the disk array control apparatus which connects a part.

FIG. 4 is a configuration diagram of a disk array controller that connects each IF unit via a mutual connection network using a switch only for the connection network of the cache memory as a connection network of the shared memory and the cache memory.

FIG. 5 is a configuration diagram of CM access control units 4a and 4b.

FIG. 6 is a configuration diagram of SM access control units 5a and 5b.

7 is a configuration diagram of a crossbar switch unit 13. FIG.

FIG. 8 is a configuration diagram of a cache memory unit 14.

FIG. 9 is a configuration diagram of a shared memory unit 15.

FIG. 10 is a sequence diagram showing a flow of access from the CM access control units 4a and 4b to the CM controller 7 when writing data to the cache memory unit 14;

11 is a sequence diagram showing a flow of access from the SM access control units 5a and 5b to the SM controller 8 when writing data to the shared memory unit 15. FIG.

FIG. 12 is a sequence diagram showing a procedure for transferring data from the SM control unit to the CM control unit by using the SM / CM path 41.

FIG. 13 is a flowchart showing an outline of the operation of the CM controller 7 of the cache memory unit 14.

[Explanation of symbols]

1 ... Disk control device, 2 ... Drive IF, 3 ... Host IF, 4 ... CM (cache memory) control unit, 5 ... SM
(Shared memory) access control unit, 6 ... Microprocessor unit, 11 ... Host IF unit, 12 ... Disk IF unit, 1
3 ... CSW (crossbar switch) unit, 14 ... Cache memory unit, 15 ... Shared memory unit, 20 ... Magnetic disk device, 31 ... CM (Cache memory) path 0, 32 ...
CM (cache memory) paths 1, 40 ... SM (shared memory memory) paths, 41 CM / SM paths, 50 host computers.

Claims (5)

[Claims] 1. A disk controller for accessing a magnetic disk device by a host computer, comprising: a host interface unit having an interface with the host computer; a disk interface unit having an interface with the magnetic disk device; A cache memory unit for temporarily storing data read / written to / from the disk device, and a shared memory unit for storing control data of the disk control device, the cache memory unit and the shared memory unit A disk control device, wherein a path for data transfer is provided between the disk control device and the control data, and the control data can be stored and accessed in the cache memory unit via the shared memory unit. 2. The connection between the cache memory unit, the host interface unit and the disk interface unit is a switch connection, and the connection between the shared memory unit, the host interface unit and the disk interface unit is a direct connection. The disk control device according to claim 1, wherein 3. The disk control device according to claim 1, wherein the connection of the shared memory unit and the cache memory unit through the data transfer path is a one-to-one connection. 4. The disk control device according to claim 1, wherein the connection of the shared memory unit and the cache memory unit through the data transfer path is a one-to-many connection. 5. A data access method of a disk controller for accessing a magnetic disk device by a host computer, wherein the disk controller comprises a host interface section having an interface with the host computer, and the magnetic disk device. A disk interface unit having an interface, a cache memory unit for temporarily storing data read / written to / from the magnetic disk device, and a shared memory unit for storing control data of the disk controller. Further, a path for data transfer is provided in the disk control device between the cache memory unit and the shared memory unit, and control data of the disk control device is transferred to the cache memory via the shared memory unit. Stored in the department Data access method for a disk controller that.