JP2000112912A - Processing system for test and copy against remote memory in distributed memory-type parallel computer - Google Patents

Abstract

PROBLEM TO BE SOLVED: To speed up a test and copy processing in a distributed memory-type parallel computer. SOLUTION: A node 1 continuously transmits a test instruction, a copy instruction and copy data. When a node 2 receives the test instruction, the copy instruction and copy data, it repetitively executes the test instruction against a remote memory in the self-node until it is succeeded. Copy data are copied to the remote memory with the copy instruction after the success of the test instruction.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a test and copy processing method for a remote memory in a distributed memory type parallel computer, and more particularly to a high speed test and copy processing method.

[0002]

2. Description of the Related Art When performing calculations using a distributed memory type parallel computer, it is desirable to perform programming (closed within the calculation nodes) so as to reduce the frequency of data transfer between nodes. This is because the calculation nodes are connected by a network, and the distance between the calculation nodes is larger than the distance within the calculation nodes. However, in large-scale science and technology problems, closed programming within each computation node is unequally possible, resulting in programming in which each computation node works in concert. For example, a case where a large-scale problem array is mapped across a plurality of nodes (mapping as a global memory space) corresponds to this.

FIG. 1 is a block diagram of a distributed memory type parallel computer.

Referring to FIG. 1, a distributed memory type parallel computer includes a plurality of calculation nodes 1/2 (for example, two nodes will be described, but the number of nodes is not limited to two). It has Network 3 connecting them. The calculation node 1 is a CPU (Central Processing Unit: Cent)
ral Processing Unit) 11, MM
U (Main storage unit: Main Memory Unit)
12. RCU (Remote control device: Remote Cont)
(Roll Unit) 13. Similarly, the calculation node 2 includes a CPU 21, an MMU 22, and an RCU 23.

In the calculation node 1, the CPU 11
Load and store data to U12,
The CPU 11 performs an operation using the loaded data, and stores the result in the MMU 12. RCU 13 uses C
It receives a data transfer instruction between the MMUs of other nodes across the calculation nodes from the PU 11, and realizes inter-node data transfer in cooperation with the RCU of the other node. For example, when the CPU 11 instructs the RCU 13 to transfer the data of the MMU 12 to the MMU 22, the RCU 13 loads the data of the MMU 12, transfers the data to the RCU 23 via the network 3, and the RCU 23 writes the transfer data to the MMU 22. This is called an inter-node write transfer. CPU1
1 instructs the RCU 13 to transfer the data of the MMU 22 to the MMU 12, the RCU 13 sends a data transfer request to the RCU 23, and the RCU 23
2 and load RCU via Network3
13 and the RCU 13 writes the transfer data to the MMU 12. This is called inter-node load transfer. At this time, the computing node 1 that has issued the instruction activation is called a local node, and the corresponding computing node 2 is called a remote node.

In FIG. 1, consider a case where a conditional copy operation extends between nodes as an example of a program. The following program tests the flag NODE2_FLAG, and if the value is "1", copies the array NODE1 (I) to the array NODE2 (I + J). Here, array NODE1 (I) is mapped to computation node 1, array NODE2 (I + J) and flag NODE2_F
Map LAG to Compute Node 2. The parent process is assumed to be the CPU of the computation node 1.

DOI = M, N IF NODE2_FLAG THEN NODE2 (I + J) = NODE1 (I) END DO In this case, the CPU of the computation node 1
For U, two instructions, a test instruction and a copy instruction, are issued. In the first test instruction, the test instruction moves between the computation nodes 1 and 2 until the test on the memory of the computation node 2 succeeds. The issuance of the copy instruction is performed after the test is successful and the CPU of the computation node 1 recognizes that the test is completed (computation node 2).
From when the test end reply is received), so that the overhead until the copy instruction is issued and the copy data arrives at the memory of the computation node 2 increases.

FIG. 6 is a block diagram showing a configuration example of a conventional RCU unit 23 (and 13), and FIG. 7 is a time chart for explaining the operation of the conventional technology.

A test and copy operation in a conventional distributed memory type parallel computer will be described with reference to FIGS. 1, 6 and 7.

First, in the local node 1, the CPU
11 to the RCU 13 using the remote memory (MMU
A test instruction for 22) is issued. In the RCU 13, the request instruction is received by the request receiving unit 1301, and after the contention arbitration with the request from the Network 3 by the contention arbitration unit 1303, the address conversion unit 1304 performs physical node number conversion / remote JOB number conversion, and performs request / data From the sending unit 1305 to the RCU 23
(Via Network 3).

Next, in the remote node 2, the RCU
23 receives a test instruction from the RCU 13 (via Network 3) in the request receiving unit 2301, and after the contention arbitration in the contention arbitration unit 2303, the address conversion unit 230.
After the physical address conversion in step 4, a test instruction is issued to the MMU 22. The test end reply from the MMU 22 is sent from the request / data sending unit 2305 to the network.
Returned to RCU 13 via rk3.

The RCU 13 determines the result, and if it fails, repeats the same test sequence. In FIG. 7, since the test sequence is successful at the third test end reply, the third test end reply is returned to the CPU 11 and the test instruction is completed.

Next, in the local node 1, the CPU
11 to the RCU 13 using the remote memory (MMU
A copy instruction for 22) is issued. In the RCU 13, the request receiving unit 1301 receives a copy command, and after the contention arbitration in the contention arbitration unit 1303, the address conversion unit 1304 converts the physical node number conversion /
The MMU 12 is accessed by performing B number conversion / physical address conversion. Then, the request / data sending unit 1305 sends the copy instruction and the load (copy) data from the MMU 12 together to the RCU 23 (via Network 3).

Next, the RCU 23 sends a copy command and copy data to the request receiving unit 2301 and the data receiving unit 2.
At 302, contention arbitration and address conversion of a copy instruction are executed by a contention arbitration unit 2303 and address conversion unit 2304, and then a copy instruction (command and address) and copy data are sent to the MMU 22 to perform write (copy).
The RCU 23 transfers the data from the RCU 13 and the MMU 2
2 is notified from the request / data sending unit 2305 to the RCU 13 via the network 3 that the write operation to the RCU 2 has been completed normally (copy end reply).
13 returns this reply to the CPU 11 to complete a series of operations.

In the configuration example shown in FIG. 6, the test and copy process (from when the CPU 11 issues a request to when it receives a reply) is completed in 80T.

[0016]

The test and copy processing in the conventional distributed memory type parallel computer described above involves
The CPU of the calculation node 1 sends the RCU of the calculation node 1
Two instructions, a test instruction and a copy instruction, are issued. In the first test instruction, the computation nodes 1 and 2 are executed until the test on the memory of the computation node 2 succeeds.
The test instruction is exchanged between the two. The issuance of the copy instruction indicates that the test succeeds and the CP
Since U recognizes the completion of the test (after receiving the test end reply from the calculation node 2), the period from when the test instruction is issued at the calculation node 1 to when the execution of the copy instruction is completed at the calculation node 2 is completed. There was a problem that overhead increased.

An object of the present invention is to provide a method for speeding up test and copy processing on a remote memory in a distributed memory type parallel computer.

[0018]

According to a first aspect of the present invention, there is provided a test and copy processing method for a remote memory in a distributed memory type parallel computer constituting a plurality of nodes in a network. A first node that sends
Upon receiving the test command, the copy command, and the copy data, execute the test command for the remote memory in the own node, and copy the copy data to the remote memory by the copy command after the execution of the test command. Characterized by having the following nodes:

According to a second aspect of the present invention, in the first aspect, the second node repeatedly executes the test instruction for the remote memory in its own node until the instruction is successful.

According to a third aspect of the present invention, there is provided a test and copy processing method for a remote memory in a distributed memory type parallel computer constituting a plurality of nodes in a network, wherein each of the nodes includes a CPU (Central Processing Unit) and an MMU (Main Unit). Storage device), RCU (remote control device)
And a first RCU at the first node
Receives a test and copy instruction from the first CPU, decomposes the instruction into a test instruction and a copy instruction, sends the test instruction to a second RCU in a second node, and subsequently transmits the test instruction and the first Sending means for sending together the copy data from the MMU to the second RCU, wherein the second RCU in the second node includes a command for storing the received test command and the received copy command. An address saving buffer, a data saving buffer for storing the received copy data, and repeatedly executing the test instruction from the command / address saving buffer and issuing to the second MMU until the test instruction succeeds. If the command succeeds, the command
A repetition control unit that fetches the copy instruction from the address save buffer and fetches the copy data from the data save buffer and issues the copy data to the second MMU.

According to a fourth aspect of the present invention, in a test and copy processing method for a remote memory in a distributed memory type parallel computer constituting a plurality of nodes in a network, a copy instruction is transmitted after transmitting a test instruction and receiving a test end reply. And a first node for continuously transmitting copy data, and upon receiving the test instruction, executing the test instruction for the remote memory in the own node, transmitting the test end reply after executing the test instruction, and terminating the test. A second node that receives the copy command and the copy data in response to the reply transmission and copies the copy data to the remote memory according to the copy command.

According to a fifth aspect of the present invention, in the fourth aspect, the second node repeatedly executes the test instruction for the remote memory in its own node until the instruction is successful.

According to a sixth aspect of the present invention, there is provided a test and copy processing method for a remote memory in a distributed memory type parallel computer constituting a plurality of nodes in a network, wherein each of the nodes includes a CPU (Central Processing Unit), an MMU (Main Unit). Storage device), RCU (remote control device)
And a first RCU at the first node
Receives a test and copy instruction from the first CPU, decomposes the instruction into a test instruction and a copy instruction, sends the test instruction to the second RCU in the second node, and receives the test end reply, And the first MMU
And sending means for sending the copy data from the second RCU together to the second RCU, wherein the second RCU in the second node comprises a command / address saving buffer for storing the received test instruction; A repetition control unit for repeatedly taking out the test instruction from the command / address save buffer and issuing the test instruction to the second MMU until the test instruction succeeds, and sending out the test end reply when the test instruction succeeds; Receiving the copy command and the copy data in response to sending the end reply and transmitting the copy command and the copy data to the second MMU
Is provided with control means for issuing the control information.

[Operation] In order to speed up the test and copy process for the remote memory in the distributed memory type parallel computer, the following two measures are taken.

1. The test instruction and the copy instruction are simultaneously issued from the CPU of the calculation node 1 by the newly installed test and copy instruction, and the test instruction, the copy instruction, and the copy data are simultaneously transferred to the calculation node 2 (sequential meaning, and so on). , Enables the execution of the copy instruction immediately after the execution of the test instruction in the computation node 2.

2. The retry sequence of the test instruction is closed in the calculation node 2 and executed (the test end reply is not returned to the calculation node 1 until the test node succeeds).

According to the first measure, the transfer time of the copy command and the copy data is hidden by the latency of the test command, and the second measure significantly reduces the turnaround time due to the retry between the calculation nodes in the test command. As a result, the speed of the test and copy processing in the distributed memory type parallel computer is increased.

[0028]

Next, embodiments of the present invention will be described in detail with reference to the drawings.

FIG. 1 is a block diagram of a distributed memory type parallel computer, FIG. 2 is a block diagram showing an example of the configuration of an RCU 23 (and 13) according to an embodiment of the present invention, and FIG.
5 is a time chart for explaining the operation of the embodiment of the present invention.

First, the configuration of the present embodiment will be described. Here, the description will focus on the RCU 23 of the remote node 2. The mapping of the array to the computation nodes is the same as the case described in the “prior art”.

Referring to FIG. 2, the request receiving unit 23
01 is a command from the CPU 21 or the RCU 13 (N
network 3), and holds the instruction. The data receiving unit 2302 is configured to execute the RCU 13 (Network
The data part transferred from 3) is received and held. The contention arbitration unit 2303 includes a request reception unit 2301
The requests inside are selected one by one (contention arbitration). The address conversion unit 2304 converts a logical node number into a physical node number, converts a local JOB number into a remote JOB number, and converts a logical address in a node into a physical address in a node. In particular, physical node number conversion and remote job
The number conversion is required for an instruction for accessing another node via Network 3, and the intra-node physical address conversion is required for an instruction for accessing the intra-node memory (here, MMU 22). Request / data sending unit 2
Reference numeral 305 denotes an instruction (command / address) after the address conversion and the load data from the MMU 22 to another node (Ne).
This is a part to be sent to the RCU 13) via the work3. The data held in the data receiving unit 2302 is stored in another node (the RCU 13 via the Network 3).
This is necessary when writing to the MMU 22 from.

Next, a command / address saving buffer 2311 and a data saving buffer 23 which are features of the present invention are described.
14, selector 2312/2315, repetition control unit 2
313 will be described. The command / address save buffer 2311 stores the MM in the test and copy instruction.
This buffer is used to save a command and an address at the time of accessing the U22, thereby enabling a test retry process (NODE2_FLAG check) to be repeatedly issued to the MMU22. The data save buffer 2314 indicates that the test was successful (NODE2_FLAG =
This buffer is for saving copy data from the local node 1 until 1), and the copy data is sent to the MMU 22 only when the test is successful. The selector 2312 normally selects the address conversion unit 2304. However, the selector 2312 selects the command / address saving buffer 2311 only at the time of test retry processing and data copy in a test and copy instruction. Selector 2315
Usually selects the data receiving unit 2302,
The data save buffer 2314 is selected only at the time of data copy processing in the test and copy instruction. The repetition control unit 2313 checks the result returned from the MMU 22 in the test retry processing of the test and copy instruction, and switches the selection direction of the selectors 2312 and 2315. The selector switching logic follows the description of the selectors 2312 and 2315.

Next, a test and copy operation in the distributed memory type parallel computer according to the present embodiment will be described with reference to FIGS. 1, 2 and 3.

First, in the local node 1, the CPU
11 to the RCU 13 using the remote memory (MMU
A test and copy instruction for 22) is issued.
In the RCU 13, the test and copy command is received by the request receiving unit 1301, and is decomposed into a test command and a copy command. The test instruction is subjected to contention arbitration in the contention arbitration unit 1303, and then to physical address number conversion / remote JOB number conversion in the address conversion unit 1304.
From the data transmission unit 1305 to the RCU 23 (Network
3). Subsequently, the copy instruction is subjected to physical arbitration in the address conversion unit 1304 after contention arbitration in the contention arbitration unit 1303, and accesses the MMU 12. Then, the request / data sending unit 1 combines the copy instruction and the load (copy) data from the MMU 12 together.
From 305, it is sent to the RCU 23 (via Network 3).

Next, in the remote node 2, the RCU
23 receives a test instruction from the RCU 13 (via Network 3) in the request receiving unit 2301, and after the contention arbitration in the contention arbitration unit 2303, the address conversion unit 230.
4, the MMU 22 converts the physical address and stores it in the command / address saving buffer 2311.
Issue to The MMU 22 repeatedly repeats the result.
13 and the test failed (NODE2_FLAG =
0), the command / address saving buffer 2311
Are repeatedly issued to the MMU 22. In FIG. 3, NODE2_FLAG = 1 at 24T.
Therefore, after failing eight times, ninth succeeds. On the other hand, during the test repetition processing, the copy instruction
(Network 3), the command and the address are received by the request receiving unit 2301, the contention is arbitrated by the contention arbitration unit 2303, and the address conversion unit 2304 is received.
After converting the physical address, the data is stored in the command / address saving buffer 2311. On the other hand, the data is received by the data receiving unit 2302 and stored in the data save buffer 2314. The copy instruction is saved in each save buffer (2311/2314) until the test is successful. Then, the test succeeds at the ninth time, and at that timing, the command and address in the command / address save buffer 2311 and the data in the data save buffer 2314 are stored in M.
The data is sent to the MU 22 for writing (copying). RCU23
Sends a notification (test and copy end reply) that the data transfer from the RCU 13 and the write operation to the MMU 22 have been normally completed from the request / data sending unit 2305 to the RCU 13 via the Network 3,
U13 returns this reply to the CPU 11, and a series of operations is completed.

Here, for convenience, the latency between / within each unit is determined as follows. NODE2_FLAG changes from “0” at 24T.
1 ", where T corresponds to one machine clock of the distributed memory type parallel computer system.

1. CPU (11, 21) / MMU (1
1. Latency between 2, 22): 1T 2. Latency between MMU (12, 22) / RCU (13, 23): 1T 3. Network (between RCU13 / RCU23) Latency: 6T At this time, in the configuration example of the present invention, the test-and-copy processing (from when the CPU 11 issues a request to when it receives a reply) is completed in 50T. In the above description of the present embodiment, Array NODE1 (I) is mapped to computation node 1, array NODE2 (I + J) and flag NODE2_F
Although the LAG is mapped to the calculation node 2, the calculation node to be mapped is not limited.

2. Although the parent process has been described as being the CPU of the computing node 1, there is no limitation on the allocation of the parent process.

3. Although the number of computing nodes connected to the network has been described as two, these numbers are not limited.

4. Although the description has been made assuming that one computation node is constituted by one CPU, the number is not limited. That is, the inside of the node may be a shared memory type using multiple CPUs.

5. Although the latencies between the units and the latencies within the units have been described using fixed values, these values are not limited.

6. There is no limit on the capacity of the command / address saving buffer.

7. There is no limit on the capacity of the data save buffer.

FIG. 4 is a diagram showing a configuration example of the RCU unit 23 (and 13) according to another embodiment of the present invention, and FIG.
9 is a time chart for explaining the operation of another embodiment.

The difference from the first embodiment of the present invention is only the RCU 23 (and 13). Also, RCU
Since the basic configuration as a unit does not change, only the command / address saving buffer 2311, selector 2312, and repetition control unit 2313, which are features of the present invention, will be described.

Command / address saving buffer 2311
Is a buffer for saving a command and an address at the time of access to the MMU 22 in a test instruction.
DE2_FLAG) can be repeatedly issued. The selector 2312 is usually
04 is selected, but the command / address saving buffer 23 is used only during the test retry processing in the test instruction.
Select 11. The repetition control unit 2313 checks the result returned from the MMU 22 and switches the selection direction of the selector 2312 in the test retry processing of the test instruction. The switching logic of the selector 2312 follows the description of the selector 2312.

Next, based on FIG. 5 (see also FIGS. 1 and 4),
A test and copy operation of the distributed memory type parallel computer according to another embodiment of the present invention will be described.

First, in the local node 1, the CPU
11 to the RCU 13 using the remote memory (MMU
A test and copy instruction for 22) is issued.
In the RCU 13, the test and copy command is received by the request receiving unit 1301, and is decomposed into a test command and a copy command. The test instruction is subjected to contention arbitration in the contention arbitration unit 1303, and is then subjected to physical node number conversion / remote JOB number conversion in the address conversion unit 1304.
Sent to 3). The copy instruction is sent to the request receiving unit 130 until the RCU 23 returns a test end reply.
It is kept at 1.

Next, in the remote node 2, the RCU
23 receives a test instruction from the RCU 13 (via Network 3) in the request receiving unit 2301, and after the contention arbitration in the contention arbitration unit 2303, the address conversion unit 230.
4, the MMU 22 converts the physical address and stores it in the command / address saving buffer 2311.
Issue to The MMU 22 repeatedly repeats the result.
13 and the test failed (NODE2_FLAG = 0)
If so, the test instruction stored in the command / address saving buffer 2311 is repeatedly issued to the MMU 22. In FIG. 5, since NODE2_FLAG = 1 at 24T, success is achieved at the ninth time after eight failures. At this timing, the request / data transmission unit 2305 sends a test end reply to the RCU 13 via the network 3.
Return to.

Next, in the RCU 13, the test end reply is received by the request receiving unit 1301, the held copy instruction is subjected to contention arbitration in the contention arbitration unit 1303, and then converted to a physical address in the address conversion unit 1304 and sent to the MMU 12 Send out. And the copy instruction and MM
The request / data sending unit 1305 combines the load (copy) data from the U12 and the RCU23 (Ne)
send to Twork3).

The RCU 23 transmits a copy command and copy data to the request receiving unit 2301 and the data receiving unit 2302.
After the contention arbitration and physical address conversion of the copy instruction are executed by the contention arbitration unit 2303 and the address conversion unit 2304, the copy instruction (command and address) and the copy data are sent to the MMU 22 to perform write (copy). R
The CU 23 transfers data from the RCU 13 and the MMU 22
The request / data sending unit 2305 sends a notification (copy end reply) that the write operation to the
Send to RCU13 via network3, RCU1
3 returns this reply to the CPU 11 to complete a series of operations.

In the configuration example shown in FIG. 4, the test and copy process (from when the CPU 11 issues a request to when it receives a reply) is completed in 64T.

In the other embodiment, the test and copy processing is slower than in the first embodiment, but the data save buffer 2314 (data save buffer 13
14) becomes unnecessary, and which one to select depends on the operating conditions of the system.

Further, it goes without saying that the present invention can be applied not only to the test and copy operation of the distributed memory type parallel computer, but also to general logic of exclusive control. For example, the present invention can be applied to speeding up a write operation on a disk.

[0055]

As described above, the present invention provides: A test instruction and a copy instruction are simultaneously issued from the CPU of the computation node 1 by a newly established test and copy instruction,
The test instruction, the copy instruction, and the copy data are transferred to the calculation node 2 at the same time.

2. The retry sequence of the test instruction is closed in the calculation node 2 and executed (the test end reply is not returned to the calculation node 1 until the test node succeeds).

By doing so, the transfer time of the copy instruction and the copy data is hidden by the latency of the test instruction, and the turnaround time due to the retry between the calculation nodes in the test instruction is greatly reduced.
As a result, there is an effect that the test and copy processing in the distributed memory type parallel computer is greatly speeded up.

[Brief description of the drawings]

FIG. 1 is a block diagram of a distributed memory parallel computer.

FIG. 2 shows an RCU 23 according to an embodiment of the present invention.
It is a block diagram showing an example of composition of (and 13).

FIG. 3 is a time chart for explaining the operation of the embodiment of the present invention.

FIG. 4 shows an RCU unit 23 according to another embodiment of the present invention.
It is a figure showing the example of composition of (and 13).

FIG. 5 is a time chart for explaining an operation of another embodiment.

FIG. 6 is a block diagram showing a configuration example of a conventional RCU unit 23 (and 13).

FIG. 7 is a time chart for explaining the operation of the conventional technique.

[Explanation of symbols]

1, 2 node 3 Network 11, 21 CPU 12, 22, MMU 13, 23 RCU 1301, 301 Request reception unit 1302, 2302 Data reception unit 1303, 2303 Competition arbitration unit 1304, 2304 Address conversion unit 1305, 2305 Request / data transmission unit 1311, 2311 Command / address saving buffer 1312, 2312 selector 1313, 2313 Repetition control unit 1314, 2314 Data saving buffer 1315, 2315 selector

Claims (6)

[Claims] In a test and copy processing method for a remote memory in a distributed memory type parallel computer constituting a plurality of nodes in a network, a first node for continuously transmitting a test instruction, a copy instruction, and copy data; When receiving the test command, the copy command and the copy data, the test command for the remote memory in the own node is executed, and after the execution of the test command, the copy command copies the copy data to the remote memory. A test and copy processing method for a remote memory in a distributed memory type parallel computer, comprising a node. 2. The remote memory-type parallel computer according to claim 1, wherein the second node repeatedly executes the test instruction for the remote memory in the own node until the instruction succeeds. Test and copy processing method for memory. 3. In a test and copy processing method for a remote memory in a distributed memory type parallel computer constituting a plurality of nodes in a network, each of the nodes includes a CPU (Central Processing Unit), an MMU (Main Storage Unit), an RCU ( The first RCU in the first node receives a test and copy instruction from the first CPU, decomposes the instruction into a test instruction and a copy instruction, and divides the test instruction into a second instruction. The copy command and the copy data from the first MMU together to send the second RC
U, and the second RCU in the second node stores a command / address saving buffer for storing the received test command and the copy command, and stores the received copy data. The data save buffer and the step of repeatedly taking out the test instruction from the command address save buffer and issuing it to the second MMU until the test instruction succeeds are repeated, and when the test instruction succeeds, the copy is executed from the command address save buffer. Fetching an instruction and fetching the copy data from the data saving buffer;
And a repetition control unit for issuing a test and copy to a remote memory in a distributed memory type parallel computer. 4. In a test and copy processing method for a remote memory in a distributed memory type parallel computer constituting a plurality of nodes in a network, a test instruction is transmitted, and a copy instruction and copy data are continuously transmitted after receiving a test end reply. A first node to transmit, upon receiving the test instruction, executing the test instruction for the remote memory in the own node, transmitting the test end reply after executing the test instruction, and responding to the test end reply according to the transmission of the test end reply. A test and copy processing method for a remote memory in a distributed memory type parallel computer, comprising: a second node that receives a copy instruction and copy data and copies the copy data to the remote memory according to the copy instruction. 5. The remote memory type parallel computer according to claim 4, wherein the second node repeatedly executes the test instruction for the remote memory in the own node until the instruction succeeds. Test and copy processing method for memory. 6. In a test and copy processing method for a remote memory in a distributed memory type parallel computer constituting a plurality of nodes in a network, each of the nodes includes a CPU (Central Processing Unit), an MMU (Main Storage Unit), an RCU ( The first RCU in the first node receives a test and copy instruction from the first CPU, decomposes the instruction into a test instruction and a copy instruction, and divides the test instruction into a second instruction. Sending means for sending to the second RCU together with the copy command and copy data from the first MMU after receiving the test end reply to the second RCU in the second node; The second RCU in the node includes a command address save buffer for storing the received test instruction, A repetition control unit that sends out the test end reply when the test instruction succeeds by repeatedly taking out the test instruction from the command / address save buffer and issuing the test instruction to the second MMU until the test instruction succeeds; And a control means for receiving the copy command and the copy data in response to the reply transmission and issuing the copy command and the copy data to the second MMU. Copy processing method.