JP2799528B2 - Multiprocessor system - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system, and more particularly to at least two processors which execute operations in parallel.
It relates to a multiprocessor system having more than one processor, each processor having a locally accessible local memory and each of the processors being interconnected via the same bus.

[0002]

2. Description of the Related Art Conventionally, various multiprocessor systems have been provided in order to speed up arithmetic processing such as numerical analysis and neural networks.

FIG. 12 is a schematic configuration diagram of a conventional multiprocessor system in which a plurality of processors are connected in parallel.

In FIG. 12, a multiprocessor system 2 includes a computing element (hereinafter, referred to as a processor) Pei (i = 0, 1, 2,..., 7) and these processors P
ei, input data bus 10 and output data bus 20
And a memory 51 accessed by the sequencer 50 and read / written by the data stored therein. Further, each of the processors Pei is connected to each other via an internal data bus 80.

The multiprocessor system 2 configured as described above has eight processors, and each processor Pei has a local memory that can be accessed independently as described later, and It is characterized in that calculations can be performed in parallel. In the multiprocessor system 2 in the case of FIG. 1, eight processors can independently and simultaneously execute arithmetic processing on one input data.

In operation, the multiprocessor system 2
Sequencer 50 sequentially reads and analyzes a program stored in advance in a memory 51, and analyzes the analyzed instruction (hereinafter, referred to as
(Referred to as a command) are sequentially applied to each of the processors Pei via the input data bus 10 in parallel. In response to this, each of the processors Pei simultaneously executes arithmetic processing according to a given command, and outputs the arithmetic result to the outside via the output data bus 20. Each of the processors Pei is configured to perform an arithmetic operation in accordance with a command given from the sequencer 50 or a command sequence stored in advance therein.

FIG. 13 is a schematic block diagram of the processor Pei shown in FIG. In FIG. 13, processor Pei includes an operation unit 1i and a local memory 3i. The arithmetic unit 1i has an adder, a register, and the like, like a general CPU (abbreviation of a central processing unit), and sequentially accesses the local memory 3i in parallel with the arithmetic processing.

The arithmetic unit 1i is connected to the sequencer 50 via the input data bus 10 and the output data bus 20, and is connected to the adjacent processor Pei via the internal data bus 80.

Here, the operation of the arithmetic processing of the processor Pei will be described. For example, it is assumed that a typical process performed by a neural network is to multiply a typical numerical value (called weight) stored in advance and input data supplied via input data bus 10.

The data read by the sequencer 50 accessing the memory 51 is provided in parallel to each of the processors Pei via the input data bus 10. In response to this, each processor Pei performs an arithmetic operation on the input data in parallel. First, the arithmetic unit 1i includes the local memory 3i
, Read the weight stored in advance, and temporarily store it in its internal register. Thereafter, the arithmetic unit 1i executes a multiplication process of the given input data and the weight stored in the internal register by using an adder, and calculates a product of the input data and the weight. Since this integration process is performed simultaneously in eight processors in parallel, there is a characteristic that an operation speed eight times as high as that of a single processor can be obtained.

[0011]

In the conventional multiprocessor system 2 as described above, the processor P
For the arithmetic processing performed by each of ei with reference to each of its own local memories 3i, a high-speed operation speed can be obtained. However, the processor Pe
In the case of processing for rearranging data stored in advance in each local memory 3i of i, there has been a problem that the processing speed is significantly reduced. For example, when executing a process of rearranging numerical data stored in the eight local memories 30 to 37 of the processors Pe0 to Pe7 in descending order, the processors Pei are stored in the local memories 3i of each other. In order to compare numerical data, the local memory 3 of its own is used.
i is stored in the internal data bus 8
0, the data is transferred to another processor Pei.
Further, each operation unit 1i of the processor Pei
Reads out the numerical data stored in the corresponding local memory 3i and performs a comparison process of the numerical data after transferring the data to another processor Pei via the internal data bus 80, so that the processing speed is reduced.

Further, as described above, the processing in which the processor Pei also refers to the data stored in the local memory 3i of another processor is significantly different from the processing in which the processor Pei refers to only the data stored in its own local memory 3i. There has been a problem that the number of steps of the program is increased and a program error is likely to occur, and the maintenance cost of the program is also increased.

It is therefore an object of the present invention to provide a multiprocessor system in which processors can arbitrarily access their local memories without increasing the number of processing program steps, thereby improving the processing speed and processing capability of the system itself. It is.

[0014]

A multiprocessor system according to the present invention has at least two or more processors connected in parallel via the same bus, and each processor performs processing in parallel. In detail, each of the processors is configured to include an arithmetic unit to which the same bus is connected, a storage unit, a bus switching unit, and the storage unit via the bus switching unit. A first bus connecting the bus switching means, a second number connecting the arithmetic means and the bus switching means, and connecting the bus switching means to the bus switching means of the other adjacent processor; And a third bus.

[0015] The arithmetic means is further configured to switch a bus based on specific data uniquely specifying the processor and parallelism data specifying the number of processors accessing the storage means in parallel, which are stored in advance therein. It comprises a signal deriving means for deriving a signal.

Further, the bus switching means further selects one of the second and third buses based on the switching signal derived by the signal deriving means and connects to the first bus. It comprises a selection means.

[0017]

The multiprocessor system according to the present invention is configured as described above, and the signal deriving means derives a bus switching signal based on the parallelism data and specific data for uniquely specifying the processor. The bus selection means selects one of the second and third buses based on the derived switching signal and connects to the first bus. Therefore, when the parallelism data is data that connects the second bus to the first bus, the storage means of the processor can be accessed by the arithmetic means of the same processor. Conversely, when the parallel degree data is data for connecting the third bus to the first bus, the storage means of the processor can be accessed by the arithmetic means of another processor via the bus switching means of the adjacent processor. Becomes As described above, only by variably setting the parallelism data, the storage means independently possessed by each processor is dynamically rearranged, and while the system configuration is fixed, each processor can perform other data transfer without performing data transfer. The storage means of the processors can be accessed, and the address space of the memory accessible for each processor is dynamically variably set.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below in detail with reference to the drawings.

In the following embodiments, a system configuration employing eight processors as a multiprocessor system is assumed. The only condition is that the number of processors constituting the system is at least two or more. There are no particular restrictions.

FIGS. 1A to 1C are system configuration diagrams for explaining an outline of a multiprocessor system 1 according to an embodiment of the present invention.

The multiprocessor system 1 shown in FIG. 1 dynamically relocates the local memory of each processor during the operation of the system so that data stored in the local memory of another processor can be stored in the processor. It is configured to be able to refer to each other without data transfer.

FIG. 1 shows a processor (calculation element) PE0.
1 to 8 are shown. FIG. 1A shows each of the processors PEi.
The local memory 3i is provided as a memory space that can be independently accessed. In the case of FIG. 1A, eight arithmetic processes can be executed in parallel as in the conventional case.

FIGS. 1B and 1C are conceptual diagrams for explaining the dynamic relocation of the local memory of the multiprocessor system according to the present embodiment.

Here, the degree of parallelism will be described. FIG.
In the multiprocessor system 1 shown in (a), there are eight processors, and all of these processors access their own memory 3i, so the degree of parallelism is 8.

In FIG. 1B, the processor PEi indicated by oblique lines is a processor that does not access its own local memory 3i. Other processors PEi are processors that access the local memory 3i. Processor PEi accessing local memory 3i as shown.
Can access the local memory 3i of the adjacent processor PEi indicated by oblique lines as if it were its own local memory. For example, the processor PE0 is connected to the adjacent processor P
This indicates that the local memory 31 of E1 can be accessed. At this time, since the number of processors PEi accessing the local memory 3i in parallel is four, the degree of parallelism is 4.

Similarly, when the degree of parallelism becomes 2 as shown in FIG. 1 (c), the processors indicated by oblique lines that do not access the local memory 3i are processors PE1, PE2, P
E3, PE5, PE6 and PE7. For example,
The processor PE0 accessing the local memory 3i is connected to the local memories 31 to 3 of the processors PE1 to PE3.
3 is accessed in the same manner as its own local memory 30.
Therefore, the accessible memory space of the processor PE0 is expanded four times as compared with the case of the normal parallelism of 8 shown in FIG. Similarly, the processor PE4 stores the local memory 3 of the processors PE5 to PE7.
5 to 37 are accessed in the same manner as the own local memory 34, and the accessible memory space of the processor PE4 is expanded to four times as compared with the case of the normal parallelism 8 shown in FIG. Is done.

Further, although not shown, when the degree of parallelism becomes 1, an accessible memory space of one processor PEi can be obtained eight times as compared with the case of the ordinary degree of parallelism of 8.

As described above, the degree of parallelism indicates the number of processors PEi that can access the local memory 3i in parallel.
It should be noted that the processor PEi shown in FIG. 1 which is not shaded and does not access the local memory 3i may operate without accessing its own local memory 3i, or may stand by without performing any operation. .

FIGS. 2A and 2B are schematic block diagrams of a processor constituting a multiprocessor system according to an embodiment of the present invention.

In FIG. 2A, the processor PEi is connected via an input data bus 10 and an output data bus 20 to
The memory 51 is connected to the connected sequencer 50.
Processor PEi further includes an arithmetic unit 1i, a memory management unit 2i, and a local memory 3i.

The operation unit 1i is connected to the sequencer 50 via the input data bus 10 and the output data bus 20. The arithmetic unit 1i is also connected to an adjacent processor via the internal data bus 80.

The memory management unit 2i includes the arithmetic unit 1
i, and via a local memory bus 40, the memory management unit 2 (i
-1) or 2 (i + 1). Local memory 3
i is connected to the memory management unit 2i. Therefore, the processor PEi is configured such that the arithmetic unit 1i accesses the local memory 3i via the memory management unit 2i.

FIG. 2B is a schematic block diagram of the arithmetic unit 1i shown in FIG. 2A. Arithmetic unit 1
i includes an instruction processing device 1a and a main storage device 1b, like a general CPU. The instruction processing device 1a includes an adder 1c and a register group 1d, operates to perform data processing according to a program (command sequence) stored in the main storage device 1b in advance, and stores the result in the main storage device 1b again. The instruction processing device 1a has an input data bus 1
0, the output data bus 20 and the internal data bus 80 are connected so that the sequencer 50 and the adjacent processor PE
i.

FIG. 3 is a schematic diagram for explaining a connection state of an input / output bus with respect to a memory management unit according to one embodiment of the present invention.

The memory management unit 2i connects an input / output bus as shown in FIG. FIG. 3 is a schematic diagram centered on the memory management unit 2i of the processor PEi. Memory management units 2 (i-1) and 2 (2) of adjacent processors
(I + 1) via the local memory bus 40. More specifically, the local memory bus 40 includes an address bus and a data bus, and the memory management units 2i and 2 (i-1) are connected via an address bus B and a data bus DB. Similarly, the memory management unit 2i and the memory management unit 2 (i + 1) are connected via an address bus Y and a data bus DY.

Further, the memory management unit 2i is connected to the arithmetic unit 1i via the address bus A and the data bus DA, and receives a bus switching signal CH from the arithmetic unit 1i. Also, the memory management unit 2i
Is a local memory 3i, an address bus X and a data bus D
X, and outputs a memory select signal MS to the local memory 3i. Memory management unit 2
i switches the connection between the address bus and the data bus to be connected as described above.

FIGS. 4A and 4B are block diagrams of the memory management unit 2i shown in FIG.

FIG. 4A shows an initial internal state of the memory management unit 2i before switching the bus connection.

In FIG. 4A, the data bus and the address bus are described together to simplify the description. Therefore, address bus A and data bus DA in FIG. 3 are described as bus A, address bus B and data bus DB are described as bus B, address bus X and data bus DX are described as bus X, and address bus Y is further described. And data bus DY is described as bus Y.

As shown in FIG. 4A, the memory management unit 2i connects the bus X connecting the local memory 3i to the bus Y in the initial state. The memory management unit 2i performs bus connection switching based on a bus switching signal CH provided from the arithmetic unit 1i. That is, the bus A is connected to the buses X and Y to connect the arithmetic unit 1i
Is switched to enable access to the local memory 3i, or the adjacent memory management unit 2 (i-
1) is connected to a bus X and a bus Y, and the adjacent processor PE (i-1)
Whether to connect the bus so that i can be accessed is selectively switched.

FIG. 4B shows a schematic block diagram of the memory management unit 2i. In FIG. 4B, the memory management unit 2i includes an address bus switch 11i, a data bus switch 12i, a mode register 13i, a pe register 14i, and a memory select determiner 15i.

The bus switch signal CH is supplied from the arithmetic unit 1i to the address bus switch 11i and the data bus switch 12i. The address bus switching unit 11i switches one of the connected address buses A and B based on the switching signal CH, and derives an address given via the switched address bus to the output side. The address derived via the address bus switch 11i is
It is provided to the adjacent memory management unit 2 (i + 1) and the local memory 3i. The data bus switch 12i connects one of the connected data buses A and B based on the supplied bus switching signal CH, and derives the data supplied from the connected data bus to the output side.
The data derived via the data bus switch 12i is
It is provided to the adjacent memory management unit 2 (i + 1) and to the local memory 3i.

As described above, the address bus switch 11i
Addresses and data derived from the data bus switch 12i are transferred to the local memory 3i and the adjacent memory management unit 2 (i + 1) via the transmission paths of the bus X and the bus Y as shown in FIG. ) Are given in parallel to both.

A command bus 10i is connected to each of the mode register 13i and the pe register 14i. The command bus 10i is not shown in FIG.
It is connected to supply a 2-bit command signal supplied from the operation unit 1i to the registers 13i and 14i. The command given via the command bus 10i is supplied from the arithmetic unit 1i to rewrite the contents of the registers 13i and 14i. Command bus 10
A 2-bit command is supplied from i. When the supplied command is "00", the mode register 13i and the pe register 14i are set to the data readable mode. When the command is "01", only the pe register 14i is set to the writable mode, the data supplied via the data bus DA is written to the register 14i, and the register contents are updated. When the applied command is "10", only the mode register 13i is set to the data writable mode.
At this time, data given via data bus DA is written into mode register 13i, and its contents are updated. If the supplied command is "11", it is assumed that the command does not occur in the multiprocessor system 1.

Memory select determiner 15i receives an address derived from the address bus switched based on bus switching signal CH, data read from mode register 13i, and data read from pe register 14i. The memory select signal MS is derived and applied to the local memory 3i. The derived memory select signal MS is a signal having one of "1" and "0" signal levels. When the memory select signal MS is at the level "1", the local memory 3i is in the writable mode. And the signal MS is at the level "0", the local memory 3i is set to the data readable mode. Therefore, the local memory 3i is stored in the memory select determiner 15i.
Only when memory select signal MS derived from the data bus is applied at signal level "1", address bus switch 11
i to the address derived from the data bus switch 12i.
It operates to write data derived from. Also,
When memory select signal MS applied from memory select determiner 15i is at signal level "0", local memory 3i operates to read data from an address derived from address bus switch 11i.

FIG. 5 is a flowchart showing the operation of selecting a connection bus in the memory management unit 2i according to one embodiment of the present invention.

In this embodiment, the processor PE
Processor number p for uniquely specifying each to i
Assume that e is pre-assigned as data. Processor numbers pe to 0 to 7 are assigned to processors PE0 to PE7 shown in FIG. 1, respectively. Also, the parallelism mode, which is variable data for determining the parallelism of the multiprocessor system 1,
Assumes that the degree of parallelism mode is assigned a value of 0, 1, 3, and 7, respectively, for each of the cases of parallelism 8, 4, 2, and 1. The data of the processor number pe and the degree of parallelism mode are stored in advance in the processor PE.
It is assumed that the data is stored in the main storage device 1b or the register group 1d of the i operation unit 1i. Further, the flow shown in FIG.
i is assumed to be stored in the main storage device 1b and executed under the control of the instruction processing device 1a.

The instruction processing device 1a reads out the program stored in the main storage device 1b, and reads the program stored in the step ST of FIG.
At 1 (abbreviated as ST1 in the figure), the processor number pe and the degree of parallelism mode stored in advance are respectively read, and it is determined whether (pe & mode) = 0 holds. The operation indicated by & is the processor number pe.
And the logical product of the parallelism mode.

In the process of step ST1, if the operation result is 0, the process proceeds to the next step ST2, and the instruction processing device 1a connects the bus A of FIG.
The bus switching signal CH is derived so as to be connected to Conversely, if the operation result is not 0 in the process of step ST1, the process proceeds to the process of step ST3 to derive a bus switching signal CH for connecting the bus B of FIG. Thereafter, the process of selecting the connection bus ends.

For example, when the multiprocessor system 1 has a parallelism of 4, the parallelism mode is (100) ₂ , so that the memory management unit 2i of the processor PEi whose processor number pe is an even number stores the bus A in the local memory. 3i so that the arithmetic unit 1i can access the local memory 3i. Also, the processor number p
The memory management unit 2i of the processor PEi where e is an odd number connects the bus B to the local memory 3i and switches the bus connection so that the processor PE (i-1) can access the local memory 3i. I do.

FIGS. 6A and 6B are schematic diagrams showing the bus connection state in the memory management unit 2i obtained according to the operation flow of FIG.

FIG. 6A shows a state where the bus A is selected by the memory management unit 2i based on the supplied bus switching signal CH and connected to the local memory 3i. FIG.
(B) shows the case where the memory management unit 2i selects the bus B based on the bus switching signal CH supplied thereto, and the processor PE
It is a figure which shows the state at the time of connecting the memory management unit 2 (i-1) of (i-1) to the local memory 3i.

By the bus connection switching operation at the degree of parallelism of 4, the processor PE whose processor number pe is an odd number
The local memory 3i of i can be referred to as the local memory 3i of the processor PEi whose processor number pe is even.

FIG. 7 is a schematic diagram showing a bus connection state in the case of a degree of parallelism of 2 obtained according to the operation flow of FIG.

In FIG. 7, when the degree of parallelism is 2, FIG.
As shown in (c), the processor PE0 including the memory management unit 20 replaces the local memories 31 to 33 with its own local memory by the bus connection switching operation of the memory management units 21, 22 and 23 shown in FIG. 3
Since it can be accessed in the same way as 0, the accessible memory space is quadrupled.

FIG. 8 is a flowchart showing a memory select operation according to one embodiment of the present invention. The flow shown in FIG. 8 corresponds to the memory select determiner 15 of each processor PEi.
The operation of i is shown. The memory select operation is an operation to derive the memory select signal MS so as to determine whether or not the local memory 3i can be accessed based on the address given by the memory select determiner 15i. In the figure, Addr3 indicates the upper three bits of the given address, and specifies the processor number pe of the processor PEi having the local memory 3i to be accessed. Therefore, in this embodiment, eight processors PE
i, the local memory 3i to be accessed is determined based on the upper 3 bits of the given address. However, the number of bits referred to is not fixed to 3 bits, and the number of processors PEi constituting the system 1 May be determined. Therefore, the address given to the memory management unit 2i is at least
It is composed of three or more bits including bits.

Next, a memory select operation according to one embodiment of the present invention will be described with reference to the flow chart of FIG.

The memory select judging unit 15i shown in FIG.
First, in the process of step ST10, (Addr
3 = pe & mode) is determined. That is, the memory select determination unit 15i
And the processor number pe and the degree of parallelism mode stored in advance from the address bus switch 11i and read the upper 3 bits A of the address given through the address bus switch 11i.
The process of step ST10 is executed together with ddr3.
At this time, if this logical expression holds, a memory select signal MS of level “1” is derived. Thus, the local memory 3i can be accessed.

Returning to the process of step ST10, if this logical expression does not hold, a memory select signal MS of level "0" is derived and applied to the local memory 3i. This makes the local memory 3i inaccessible.

FIG. 9 is a schematic diagram showing an example of a memory select state in the case of a parallelism of 2 obtained according to the operation flow of FIG.

Now, the input data bus 1 from the sequencer 50
It is assumed that the same address has been given to all the processors PEi through “0”.

When the upper 3 bits of the address are 2, that is, Addr3 = (10) ₂ , only the memory select signal MS of the processor PE2 is at the level “1” as shown in FIG. Establishes a connection bus with the memory management unit 22. Therefore, the processor PE0 can access the local memory 32 based on the given address in the memory space expanded four times.

As described above, each processor PEi
Selects a bus to be connected to its own local memory 3i according to the processor number pe and the parallelism mode at that time according to the operation flow shown in FIG. Further, according to the processing flow of FIG. 8, based on the given address, the value of the upper three bits Addr3,
Based on the processor number pe and the degree of parallelism mode, it is determined which of the local memories constituting the memory space extended by the current degree of parallelism is to be accessed. Thereby, each of the processors PEi can access using the address given the expanded memory space according to the degree of parallelism.

FIG. 10 is a schematic diagram for explaining a state in which only the data bus is switched in connection with the memory management unit 2i according to one embodiment of the present invention.

In the above embodiment, the memory management unit 2i has a structure in which both the address bus and the data bus are switched. However, a simple structure in which only the data bus is switched can be realized in the same manner as described above. It is possible.

As shown in FIG. 10, in this case, the address for accessing local memory 3i is always given from the corresponding arithmetic unit 1i. However, when the address for accessing the memory changes during execution of the operation (dynamically changes), there is a limitation that the memory cannot be accessed with the simple structure shown in FIG. For example, when the processor PE0 attempts to access the local memory 31 of the adjacent processor PE1 and an address for memory reference is described in a command stored in the memory 51, the simple structure is used. Can access the memory.
That is, the sequencer 50 sends commands to be sequentially read from the memory 51 to the processor PE via the input data bus 10.
0 and PE1 at the same time.
And 11 receive the same command at the same time and simultaneously supply address signals to their own local memories 30 and 31, so that the processor PE0 can access the local memory 31 of the adjacent processor PE1. However, if the same command is not given all at once via the sequencer 50 but an address for memory access is stored in, for example, the register group 1d of the processor PE0, the adjacent processor PE0
Since 1 cannot refer to the address stored therein, it cannot provide an appropriate address signal to its local memory 31.

As described above, in the case where the multiprocessor system 1 operates according to only the command sequence previously stored in the memory 51 via the sequencer 50, the same command is given to all processors at once. A desired memory space can be accessed using a simple structure for switching only the data bus as shown in FIG.

In the multiprocessor system 1, a command given from the sequencer 50 and each processor PE
In the case where the processing is executed in accordance with the command stored in the register group 1d inside i, a structure for switching the connection between the data bus and the address bus as shown in FIG. To be accessible.

As described above, according to the supply format of the command for controlling the operation of the processor system 1, the method of switching connection of only the data bus or the method of switching connection of the data bus and the address bus simultaneously is selected. Is also good.

FIG. 11 is a flowchart showing a variable parallelism setting operation of the multiprocessor system according to the embodiment of the present invention.

The illustrated flow is stored as a program in advance in each main storage device 1b of the processor PEi and executed under the control of the instruction processing device 1a.
Alternatively, the program is stored in the memory 51 in advance as a program,
The data may be sequentially read out and executed under the control of the sequencer 50.

In the above-described embodiment, the parallelism mode of the multiprocessor system 1 is set in advance as fixed data in each of the processors PEi. However, the parallelism mode may be variably set. That is, when the address given or generated during execution exceeds the address space of the memory that can be accessed by itself, each processor PEi sets a value that reduces the current parallelism in the parallelism mode accordingly. , Data stored at a desired address can be read from the memory. This allows the user to perform programming without being aware of the degree of parallelism of the multiprocessor system 1.

Now, the multiprocessor system 1 will be described with reference to FIG.
As shown in (a), the parallelism is 8, ie, the parallelism mo
Assume that de = 0. The processor PEi
Are stored in the local memory 3i in the main storage device 1b.
It is assumed that the size S of the memory space is stored in advance as data.

The sequencer 50 decodes a program stored in the memory 51 to obtain address data add obtained by decoding the program.
r through input data bus 10 to all processors P
Give to Ei all at once.

Each operation unit 1i of processor PEi receives the given address data addr, and executes the process of step ST20 in FIG. 11 in response. In the process of step ST20, the instruction processing device 1
a temporarily stores the given address data addr in its register group 1d, and stores the address data addr in the main storage device 1d.
b, the size S of the local memory space is read, and (addr
≧ S) is determined. At this time, if it is determined that this logical expression is not satisfied, that is, the given address data addr specifies the memory space of its own local memory 3i, the process proceeds to the next step ST21, and the instruction processing device 1a A value of 0 is set in the parallelism mode of the main storage device 1b.
Is set, and the process ends. Thereby, the degree of parallelism of the multiprocessor system 1 is maintained at 8, and each of the processors PEi receives the given address data addr.
, Desired data can be read and written from and to its own local memory 3i by specifying an address.

Returning to the process of step ST20, the instruction processing device 1a determines that (addr ≧ S) holds, that is, the given address data addr exceeds the size of the memory space of its own local memory 3i. If it is determined that the operation has been performed, the process proceeds to the next step ST22.

In the process of step ST22, the instruction processing device 1a sets the value 1 to the data mode of the main storage device 1b, and lowers the degree of parallelism of the multiprocessor system 1 to 4. As a result, a system configuration as shown in FIG. 1A to FIG. 1B is obtained, and the processor PEi having the even processor number pe is a local processor of the adjacent processor PEi having the odd odd processor number pe. By accessing the memory 3i as its own memory space, desired data can be read and written using the given address data addr.

As described in this embodiment, the multiprocessor system 1 has 2 ⁿ (= N) processors, so that the degree of parallelism is reduced to N / 2 or N / 4. Even in this case, since the symmetry of the system configuration is maintained, the control can be performed efficiently.

[0079]

As described above, according to the present invention, the signal deriving means derives the bus switching signal based on the parallelism data and the specific data for uniquely specifying the processor.
The bus selecting means operates to connect one of the second and third buses to the first bus based on the derived bus switching signal. Second bus is first according to parallel degree data
When connected to the bus, the storage means of the processor is set so as to be accessible by the arithmetic means of the same processor. Conversely, when the third bus is connected to the first bus, the storage means of the processor is set. Is set to be accessible by arithmetic means of another processor except the processor via the bus switching means of the adjacent processor. Therefore, in the multiprocessor system according to the present invention, it is possible to dynamically rearrange the storage means independently accessed by each processor by merely arbitrarily setting the parallelism data without increasing the number of program steps. This has the effect of becoming

The effect described above is that, while the system configuration is fixed, each processor accesses the storage means of another processor without transferring data between the processors via the bus switched by the bus switching means. This makes it possible to arbitrarily and flexibly set the address space of the local memory accessible to each processor.

Further, the effect as described above brings about an effect that the processing speed and processing capability of each processor, and furthermore, the multiprocessor system itself can be improved.

[Brief description of the drawings]

FIGS. 1A to 1C are system configuration diagrams for explaining an outline of a multiprocessor system according to a first embodiment of the present invention.

FIGS. 2A and 2B are schematic block diagrams of a processor constituting a multiprocessor system according to an embodiment of the present invention.

FIG. 3 is a schematic diagram for explaining a connection state of an input / output bus with respect to a memory management unit according to one embodiment of the present invention.

FIGS. 4A and 4B are block diagrams of the memory management unit shown in FIG. 3;

FIG. 5 is a flowchart showing an operation of selecting a connection bus in a memory management unit according to an embodiment of the present invention.

FIGS. 6A and 6B are schematic diagrams showing bus connection states in a memory management unit obtained according to the operation flow of FIG. 5;

7 is a schematic diagram showing a bus connection state in the case of a degree of parallelism of 2 obtained according to the operation flow of FIG. 5;

FIG. 8 is a flowchart showing a memory select operation according to an embodiment of the present invention.

9 is a schematic diagram illustrating an example of a memory select state in the case of a parallelism of 2 obtained according to the operation flow of FIG. 8;

FIG. 10 is a schematic diagram illustrating a state in which only a data bus is switched in connection with a memory management unit according to an embodiment of the present invention;

FIG. 11 is a flowchart showing an operation of variably setting the degree of parallelism of the multiprocessor system according to one embodiment of the present invention.

FIG. 12 is a schematic configuration diagram of a conventional multiplexer system in which a plurality of processors are connected in parallel.

13 is a schematic configuration diagram of the processor shown in FIG.

[Explanation of symbols]

 Reference Signs List 1 multiprocessor system PEi processor (computing element) 1i arithmetic unit 2i memory management unit 3i local memory 10 input data bus 20 output data bus 40 local memory bus 50 sequencer 51 memory 80 internal data bus CH bus switching signal MS memory select signal pe Processor number mode Parallelism Addr3 Upper 3 bits of address S Size of local memory space (i = 0, 1, 2,..., 7) In the drawings, the same reference numerals indicate the same or corresponding parts.

Claims (1)

(57) [Claims] 1. A multiprocessor system having at least two or more processors connected in parallel via a same bus, wherein each processor performs processing in parallel, wherein each of the processors is connected to the same bus. Computing means, storage means, bus switching means, and a first means for connecting the storage means and the bus switching means of one of the adjacent processors via the bus switching means.
A second bus connecting the arithmetic unit and the bus switching unit; a third bus connecting the bus switching unit and the bus switching unit of the other adjacent processor; The arithmetic unit further includes a signal deriving unit that derives a bus switching signal based on specific data uniquely identifying the processor and parallelism data stored in advance therein, and the bus switching unit further includes: Based on the switching signal derived by the signal deriving means, the second and third
A multi-processor, comprising: bus selection means for selecting any one of the buses and connecting to the first bus; wherein the parallelism data is data for specifying the number of processors that access the storage means in parallel. system.