JPH0554008A - Multiprocessor system - Google Patents

Abstract

PURPOSE:To provide a multiprocessor system where processors arbitrarily access local memories of processors of one another to increase the processing speed and the processing capability without increasing the number of processing program steps. CONSTITUTION:A multiprocessor system 1 includes plural processors PEi, and each processor PEi is provided with a local memory 3i which is accessible independently. Local memories 3i are dynamically rearranged in accordance with a set degree of parallel so that processors PEi which perform the memory access processing can refer to local memories of processors PEi which do not perform the memory access processing, and the memory space which each processor PEi is accessible is extended without changing the program.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a multiprocessor system, and more particularly to at least two processors that execute operations in parallel.
The present invention relates to a multiprocessor system having at least two processors, each processor having a locally accessible memory, and each processor being mutually connected via the same bus.

[0002]

2. Description of the Related Art Conventionally, various multiprocessor systems have been provided in order to speed up arithmetic processing such as numerical analysis and neural networks.

FIG. 12 is a schematic configuration diagram of a conventional multiprocessor system in which a plurality of processors are connected in parallel.

In FIG. 12, a multiprocessor system 2 includes computing elements (hereinafter, referred to as processors) Pei (hereinafter, i = 0, 1, 2, ..., 7) and these processors P.
ei, input data bus 10 and output data bus 20
A sequencer 50 connected in parallel via the memory and a memory 51 for reading and writing data stored and stored therein. Further, the processors Pei are connected to each other via an internal data bus 80.

The multiprocessor system 2 configured as described above has eight processors, and each processor Pei has a local memory that can be independently accessed as will be described later. It is characterized in that it can execute operations in parallel. In the multiprocessor system 2 in the case of FIG. 1, eight processors can independently and simultaneously perform arithmetic processing on one input data.

In operation, the multiprocessor system 2
Sequencer 50 sequentially reads and analyzes a program stored in advance in memory 51, and analyzes the analyzed instruction (hereinafter,
Command) is sequentially given to each of the processors Pei in parallel via the input data bus 10. In response to this, each of the processors Pei simultaneously executes the arithmetic processing according to the given command, and outputs the arithmetic result to the outside via the output data bus 20. Further, each of the processors Pei is configured to perform an arithmetic processing operation in accordance with a command given from the sequencer 50 or a command sequence stored therein beforehand.

FIG. 13 is a schematic block diagram of the processor Pei shown in FIG. In FIG. 13, the processor Pei includes an arithmetic unit 1i and a local memory 3i. The arithmetic unit 1i has an adder, a register and the like like a general CPU (abbreviation of central processing unit), and sequentially accesses the local memory 3i in parallel with arithmetic processing.

The arithmetic unit 1i is connected to the sequencer 50 via the input data bus 10 and the output data bus 20, and is also connected to the adjacent processor Pei via the internal data bus 80.

Now, the operation of the arithmetic processing of the processor Pei will be described. For example, it is assumed that a neural network performs a typical multiplication process of a numerical value (called a weight) stored in advance inside and input data given via the input data bus 10.

The sequencer 50 accesses the memory 51 and applies the read data to the processors Pei in parallel via the input data bus 10. In response to this, each processor Pei executes arithmetic processing on the input data in parallel. First, the arithmetic unit 1i includes the local memory 3i.
To read the previously stored wait and temporarily store it in the internal register. After that, the arithmetic unit 1i uses the adder to perform the multiplication process of the supplied input data and the weight stored in the internal register, and calculates the product of the input data and the weight. Since this integration processing is performed in parallel in eight processors at the same time, there is a feature that an operation speed that is eight times higher than that in the case of a single processor can be obtained.

[0011]

In the conventional multiprocessor system 2 as described above, the processor P
It is possible to obtain a high calculation speed for the calculation processing performed by each ei while referring to each of its own local memories 3i. However, the processor Pe
In the case of processing for rearranging the data stored in advance in the respective local memories 3i of i, there is a problem that the processing speed is significantly reduced. For example, when executing a process of rearranging numerical data stored in the eight local memories 30 to 37 of the processors Pe0 to Pe7 in descending order, the processors Pei are stored in the local memories 3i of each other. In order to compare the numerical data, its own local memory 3
The numerical data stored in i is stored in the internal data bus 8
Data is transferred to another processor Pei via 0.
Further, each arithmetic unit 1i of the processor Pei
Reads numerical data stored in the corresponding local memory 3i, transfers the data to another processor Pei via the internal data bus 80, and then compares the numerical data, so that the processing speed is reduced.

Further, as described above, the processing in which the processor Pei also refers to the data stored in the local memory 3i of another processor is remarkably higher than the processing in which only the data stored in its own local memory 3i is referred to. There is also a problem that the number of steps of the program increases, a program error is likely to occur, and the maintenance cost of the program also increases.

Therefore, an object of the present invention is to provide a multiprocessor system in which the local memory of each processor is arbitrarily accessed by each processor without increasing the number of processing program steps to improve the processing speed and processing capacity of the system itself. Is.

[0014]

A multiprocessor system according to the present invention is a system that has at least two processors connected in parallel via the same bus, and each processor processes in parallel. In detail, each of the processors is connected to the same bus, an arithmetic means, a storage means, a bus switching means, and the storage means via the bus switching means. A first bus connecting the bus switching means, a second number connecting the arithmetic means and the bus switching means, the bus switching means, and the bus switching means of the other adjacent processor are connected. And a third bus that operates.

The arithmetic means further switches the bus based on specific data for uniquely identifying the processor and parallelism data for identifying the number of the processors accessing the storage means in parallel, which are internally stored in advance. It is configured to include signal deriving means for deriving a signal.

The bus switching means further selects one of the second and third buses based on the switching signal derived by the signal deriving means and connects the bus to the first bus. It is configured to include a selection unit.

[0017]

The multiprocessor system according to the present invention is constructed as described above, and the signal deriving means derives the bus switching signal based on the parallelism data and the specific data for uniquely identifying the processor. The bus selection means selects one of the second and third buses based on the derived switching signal and connects the selected bus to the first bus. Therefore, when the parallelism data is data for connecting the second bus to the first bus, the storage means of the processor can be accessed by the arithmetic means of the same processor. On the contrary, when the parallelism data is data for connecting the third bus to the first bus, the storage means of the processor can be accessed by the arithmetic means of another processor via the bus switching means of the adjacent processor. Becomes As described above, simply by variably setting the parallelism data, the storage means unique to each processor is dynamically rearranged, and while the system configuration is fixed, each processor does not perform data transfer and other The storage means of the processor can be accessed, and the accessible address space of the memory for each processor is dynamically set.

[0018]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described in detail below with reference to the drawings.

In the following embodiments, a system configuration in which eight processors are adopted as a multiprocessor system is assumed, but the only condition is that the number of processors constituting the system is at least two or more. There are no particular restrictions.

1 (a) to 1 (c) are system configuration diagrams for explaining the outline of a multiprocessor system 1 according to an embodiment of the present invention.

The multiprocessor system 1 shown in FIG. 1 dynamically relocates the local memory of each of the processors during the operation of the system so that the data stored in the local memory of another processor can be processed by the processor. It is configured so that they can be referred to without mutual data transfer.

FIG. 1 shows a processor (computing element) PE0.
A system configured to include eight of PE to PE7 is shown. In FIG. 1A, each of the processors PEi
The local memory 3i is provided as a memory space that can be independently accessed. In the case of FIG. 1A, eight arithmetic processings can be executed in parallel as in the conventional case.

FIGS. 1B and 1C are conceptual diagrams for explaining the dynamic relocation of local memory in the multiprocessor system according to this embodiment.

Here, the degree of parallelism will be described. Figure 1
In the multiprocessor system 1 shown in (a), there are eight processors, and all of these processors access their own memory 3i, so the degree of parallelism is eight.

In the case of FIG. 1B, the shaded processor PEi is a processor that does not access its own local memory 3i. The other processors PEi are processors that access the local memory 3i. Processor PEi accessing local memory 3i as shown
Can access the local memory 3i of the processor PEi indicated by the adjacent diagonal lines as if it were its own local memory. For example, the processor PE0 is adjacent to the processor P0 in the same manner as its own local memory 30.
It shows that the local memory 31 of E1 can be accessed. At this time, since the number of processors PEi that access the local memory 3i in parallel is four, the parallel degree is 4.

Similarly, when the degree of parallelism is 2 as shown in FIG. 1C, the processors PE1, PE2, P2 that are indicated by diagonal lines and do not access the local memory 3i are processors PE1, PE2, P2.
E3, PE5, PE6 and PE7. For example,
The processor PE0 that accesses the local memory 3i has the local memories 31 to 3 of the processors PE1 to PE3.
3 is accessed in the same manner as its own local memory 30.
Therefore, the accessible memory space of the processor PE0 is expanded four times as compared with the case of the normal parallel degree of 8 shown in FIG. Similarly, the processor PE4 is the local memory 3 of the processors PE5 to PE7.
5 to 37 are accessed in the same manner as the local memory 34 of its own, and the accessible memory space of the processor PE4 is expanded four times as compared with the case of the normal parallel degree of 8 shown in FIG. To be done.

Further, although not shown, when the degree of parallelism is 1, it is possible to obtain 8 times as much accessible memory space for one processor PEi as in the case of the normal degree of parallelism 8.

As described above, the degree of parallelism indicates the number of processors PEi that can access the local memory 3i in parallel.
It should be noted that the processor PEi indicated by hatching that does not access the local memory 3i shown in FIG. 1 may perform an operation of not accessing its own local memory 3i, or may be in a standby state without performing any operation. ..

2 (a) and 2 (b) are schematic block diagrams of processors constituting a multiprocessor system according to an embodiment of the present invention.

In FIG. 2A, the processor PEi passes through the input data bus 10 and the output data bus 20,
It is connected to the sequencer 50 to which the memory 51 is connected.
The processor PEi further includes an arithmetic unit 1i, a memory management unit 2i and a local memory 3i.

The arithmetic unit 1i is connected to the sequencer 50 via the input data bus 10 and the output data bus 20. The arithmetic unit 1i is also connected to an adjacent processor via the internal data bus 80.

The memory management unit 2i is the arithmetic unit 1
The memory management unit 2 (i) of the processor connected to the i and also adjacent via the local memory bus 40.
-1) or 2 (i + 1). Local memory 3
i is connected to the memory management unit 2i. Therefore, the processor PEi is configured so that the arithmetic unit 1i accesses the local memory 3i via the memory management unit 2i.

FIG. 2 (b) is a schematic block diagram of the arithmetic unit 1i shown in FIG. 2 (a). Arithmetic unit 1
i includes an instruction processing device 1a and a main storage device 1b, like a general CPU. The instruction processing device 1a includes an adder 1c and a register group 1d, and operates so as to process data according to a program (command sequence) stored in the main storage device 1b in advance and store the result in the main storage device 1b again. Further, the instruction processing device 1a has an input data bus 1
0, the output data bus 20 and the internal data bus 80 are connected, and the sequencer 50 and the adjacent processor PE are connected.
configured to be connected to i.

FIG. 3 is a schematic diagram for explaining a connection state of the input / output bus related to the memory management unit according to the embodiment of the present invention.

The memory management unit 2i connects the input / output buses as shown in FIG. In FIG. 3, a schematic diagram focusing on the memory management unit 2i of the processor PEi is shown. The memory management unit 2i includes the memory management units 2 (i-1) and 2 of the adjacent processors.
(I + 1) is connected via the local memory bus 40. Specifically, the local memory bus 40 is configured to include an address bus and a data bus, and the memory management units 2i and 2 (i-1) are connected via the address bus B and the data bus DB. Similarly, the memory management unit 2i and the memory management unit 2 (i + 1) are connected via the address bus Y and the data bus DY.

Further, the memory management unit 2i is connected to the arithmetic unit 1i via the address bus A and the data bus DA, and receives a bus switching signal CH from the arithmetic unit 1i. Also, the memory management unit 2i
Is a local memory 3i, an address bus X and a data bus D
It is connected via X and outputs a memory select signal MS to the local memory 3i. Memory management unit 2
i switches the connection between the address bus and the data bus to be connected as described above.

FIGS. 4A and 4B are block diagrams of the memory management unit 2i shown in FIG.

FIG. 4A shows the initial internal state of the memory management unit 2i before switching the bus connection.

In FIG. 4A, the data bus and the address bus are described together for the sake of simplicity. Therefore, address bus A and data bus DA in FIG. 3 are described as bus A, address bus B and data bus DB are described as bus B, address bus X and data bus DX are described as bus X, and address bus Y is further described. The data bus DY is described as a bus Y.

As shown in FIG. 4A, the memory management unit 2i connects the bus X connecting the local memory 3i to the bus Y in the initial state. The memory management unit 2i switches the bus connection based on the bus switching signal CH provided from the arithmetic unit 1i. That is, the bus A is connected to the bus X and the bus Y to connect the arithmetic unit 1i.
Connection switching so that the local memory 3i can be accessed, or the adjacent memory management unit 2 (i-
1) is connected to the bus X and the bus Y so that the adjacent processor PE (i-1) has the local memory 3
The bus is connected so that i can be accessed selectively.

FIG. 4B shows a schematic block of the memory management unit 2i. In FIG. 4B, the memory management unit 2i includes an address bus switch 11i, a data bus switch 12i, a mode register 13i, a pe register 14i and a memory select determiner 15i.

A bus switching signal CH is applied from the arithmetic unit 1i to the address bus switching unit 11i and the data bus switching unit 12i. The address bus switch 11i switches either one of the connected address buses A and B based on the switching signal CH, and derives the address given via the switched address bus to the output side. The address derived via the address bus switch 11i is
It is provided to the adjacent memory management unit 2 (i + 1) and the local memory 3i. The data bus switcher 12i connects either one of the connected data buses A and B based on the supplied bus switch signal CH, and derives the data supplied from the connected data bus to the output side.
The data derived via the data bus switch 12i is
It is given to the adjacent memory management unit 2 (i + 1) and is given to the local memory 3i.

As described above, the address bus switch 11i
The address and data derived from the data bus switcher 12i and the local memory 3i and the adjacent memory management unit 2 (i + 1) are transmitted through the transmission paths of the bus X and the bus Y as shown in FIG. ) Is given in parallel to both.

A command bus 10i is connected to each of the mode register 13i and the pe register 14i. Although the command bus 10i is not shown in FIG. 3 above,
It is connected to apply a 2-bit command signal provided from the arithmetic unit 1i to the registers 13i and 14i. The command given via the command bus 10i is supplied from the arithmetic unit 1i to rewrite the contents of the registers 13i and 14i. Command bus 10
A 2-bit command is supplied from i. When this supply command is "00", the mode register 13i and pe register 14i are set to the data readable mode. When the command is "01", only the pe register 14i is set to the writable mode, the data given via the data bus DA is written in the register 14i, and the content of the register is updated. When the applied command is "10", only the mode register 13i is set to the data writable mode.
At this time, the data given via the data bus DA is written in the mode register 13i, and the content thereof is updated. When the supplied command is "11", it is assumed that it does not occur in the multiprocessor system 1.

The memory select determiner 15i receives an address derived from the address bus switched based on the bus switching signal CH, data read from the mode register 13i and data read from the pe register 14i, and in response thereto. The memory select signal MS is derived and given to the local memory 3i. The derived memory select signal MS is a signal having a signal level of either "1" or "0". When the memory select signal MS is at level "1", the local memory 3i is in the writable mode. And the signal MS is at level "0", the local memory 3i is set to the data readable mode. Therefore, the local memory 3i is the memory select determiner 15i.
Only when the memory select signal MS derived from is given at the signal level "1", the address bus switch 11
to the address derived from i, the data bus switch 12i
Operates to write data derived from. Also,
When the memory select signal MS provided from the memory select determiner 15i has a signal level "0", the local memory 3i operates to read data from the address derived from the address bus switch 11i.

FIG. 5 is a flow chart showing a connection bus selecting operation in the memory management unit 2i according to the embodiment of the present invention.

In the present embodiment, the processor PE
The processor number p for uniquely identifying each i
It is assumed that e is pre-allocated as data. For the processors PE0 to PE7 shown in FIG. 1, 0 to 7 are assigned to the processor numbers pe. In addition, the parallelism mode which is variable data that determines the parallelism of the multiprocessor system 1.
Assumes that for each of the parallelism levels of 8, 4, 2 and 1, the parallelism mode is assigned a value of 0, 1, 3 and 7, respectively. Each data of the processor number pe and the parallelism mode is previously stored in the processor PE.
It is assumed that the data is stored in the main storage device 1b or the register group 1d of the arithmetic unit 1i of i. Moreover, the flow shown in FIG.
Suppose that i is stored in the main storage device 1b and executed under the control of the instruction processing device 1a.

The instruction processing device 1a reads the program stored in the main storage device 1b, and the step ST of FIG.
In 1 (abbreviated as ST1 in the figure), the processor number pe and the parallelism mode that are stored in advance are read out to determine whether (pe & mode) = 0 holds. The operation indicated by & is the processor number pe
And the parallel degree mode.

In the process of step ST1, if the operation result is 0, the process proceeds to the next step ST2, and the instruction processing device 1a connects the bus A of FIG. 4A to the buses X and Y.
The bus switching signal CH is derived so as to be connected to. On the contrary, if the calculation result is not 0 in the process of step ST1, the process shifts to the process of step ST3, and the bus switching signal CH for connecting the bus B of FIG. 4A to the buses X and Y is derived. After that, the connection bus selection processing ends.

For example, when the multiprocessor system 1 has a parallel degree of 4, the parallel degree mode is (100) _2. Therefore, the memory management unit 2i of the processor PEi having the even processor number pe uses the bus A as a local memory. 3i so that the arithmetic unit 1i can access the local memory 3i. Also, the processor number p
The memory management unit 2i of the processor PEi in which e is an odd number connects the bus B to the local memory 3i and switches the connection of the bus so that the local memory 3i of the processor PE (i-1) can be accessed. I'm doing it.

FIGS. 6A and 6B are schematic diagrams showing bus connection states in the memory management unit 2i obtained according to the operation flow shown in FIG.

FIG. 6A shows a state in which the bus A is selected based on the bus switching signal CH provided by the memory management unit 2i and connected to the local memory 3i. Figure 6
(B) shows that the memory management unit 2i selects the bus B based on the bus switching signal CH and the processor PE
It is a figure which shows the state at the time of connecting the memory management unit 2 (i-1) of (i-1) to the local memory 3i.

Due to the bus connection switching operation at the parallel degree of 4, the processor PE whose processor number pe is an odd number
The local memory 3i of i can be referred to as the local memory 3i of the processor PEi having the even processor number pe.

FIG. 7 is a schematic diagram showing a bus connection state in the case of parallelism of 2 obtained according to the operation flow of FIG.

In FIG. 7, when the degree of parallelism is 2, FIG.
As shown in (c), the processor PE0 including the memory management unit 20 causes the local memories 31 to 33 to move their own local memories by the bus connection switching operation shown in FIG. 5 in the memory management units 21, 22 and 23. Three
Since it can be accessed in the same way as 0, the accessible memory space is expanded four times.

FIG. 8 is a flow chart showing a memory select operation according to an embodiment of the present invention. The flow shown in FIG. 8 is performed by the memory select determiner 15 of each processor PEi.
The operation of i is shown. The memory select operation is an operation for deriving the memory select signal MS so as to determine whether or not the local memory 3i can be accessed based on the address given by the memory select determiner 15i. Addr3 in the figure indicates the upper 3 bits of the given address, which specifies the processor number pe of the processor PEi having the local memory 3i to be accessed. Therefore, in this embodiment, the eight processors PE
Since i is connected, the local memory 3i to be accessed is determined based on the upper 3 bits of the given address, but the number of bits to be referred is not fixed to 3 bits, but the number of processors PEi configuring the system 1 It may be determined depending on. Therefore, the address given to the memory management unit 2i should be at least this upper 3
It consists of 3 bits or more including bits.

Next, the memory select operation according to the embodiment of the present invention will be described with reference to the flow chart of FIG.

The memory select determiner 15i of FIG. 4 (b)
First, in the processing of step ST10, (Addr
3 = pe & mode) is established. That is, the memory select determiner 15i uses the register 14i
And 13i, the prestored processor number pe and parallelism mode are read, and the upper 3 bits A of the address given via the address bus switcher 11i
The processing of step ST10 is executed together with ddr3.
At this time, if this logical expression is satisfied, the memory select signal MS of level "1" is derived. As a result, the local memory 3i is accessible.

Returning to the processing of step ST10, if this logical expression is not satisfied, the memory select signal MS of level "0" is derived and given to the local memory 3i. This makes the local memory 3i inaccessible.

FIG. 9 is a schematic diagram showing an example of the memory select state in the case of the parallel degree 2 obtained according to the operation flow of FIG.

Now, input data bus 1 from sequencer 50
It is assumed that the same address is given to all processors PEi via 0.

When the upper 3 bits of the address are 2, that is, Addr3 = (10) ₂ , only the memory select signal MS of the processor PE2 is in the level "1" state and only the local memory 32 is shown in FIG. Establishes a connection bus with the memory management unit 22. Therefore, the processor PE0 can access the local memory 32 based on the given address in the memory space expanded four times.

As described above, each processor PEi
In accordance with the operation flow shown in FIG. 5, the bus to be connected to its own local memory 3i is selected and connection switched according to the processor number pe and the parallel degree mode at that time. Further, according to the processing flow of FIG. 8, based on the given address, the value of the upper 3 bits Addr3,
Based on the processor number pe and the parallelism mode described above, it is determined which of the local memories configuring the memory space expanded by the current parallelism is to be accessed. As a result, each of the processors PEi can access the expanded memory space by using an address provided in accordance with the degree of parallelism.

FIG. 10 is a schematic diagram for explaining a state in which only the data bus is connected and switched in the memory management unit 2i according to the embodiment of the present invention.

In the above-described embodiment, the memory management unit 2i has a structure in which both the address bus and the data bus are connected and switched, but a simple structure in which only the data bus is switched can be realized in the same manner as that described above. It is possible.

As shown in FIG. 10, in this case, the address for accessing the local memory 3i is always given from the corresponding arithmetic unit 1i. However, if the address for accessing the memory changes (dynamically changes) during execution of the operation, the simple structure shown in FIG. 10 has a limitation that the memory cannot be accessed. For example, when the processor PE0 attempts to access the local memory 31 of the adjacent processor PE1, when the address for memory reference is described in the command stored in the memory 51, this simplified structure is used. You can access the memory with.
That is, the sequencer 50 sends a command for sequentially reading from the memory 51 to the processor PE via the input data bus 10.
0 and PE1 are given at the same time, so the arithmetic unit 10
And 11 simultaneously receive the same command, and at the same time, give address signals to their own local memories 30 and 31, so that the processor PE0 can access the local memory 31 of the adjacent processor PE1. However, if the same command is not given all at once via the sequencer 50, but an address for memory access is stored in, for example, the register group 1d of the processor PE0, the adjacent processors PE
Since 1 cannot refer to the address stored therein, it cannot give an appropriate address signal to its own local memory 31.

As described above, in the case where the multiprocessor system 1 operates according to only the command sequence stored in the memory 51 in advance via the sequencer 50, the same command is given to all the processors at once. The desired memory space can be accessed by using the simple structure shown in FIG. 10 in which only the data bus is connected and switched.

In the multiprocessor system 1, a command given from the sequencer 50 and each processor PE
When the processing is executed in accordance with the command stored in the register group 1d inside i, the structure for switching the connection between the data bus and the address bus is adopted as shown in FIG. To be accessible.

As described above, depending on the supply format of the command for controlling the operation of the processor system 1, the method of switching the connection of only the data bus or the method of simultaneously switching the connection of the data bus and the address bus is used. Good.

FIG. 11 is a flow chart showing the variable parallel degree setting operation of the multiprocessor system according to the embodiment of the present invention.

The flow shown in the figure is stored as a program in each main memory 1b of the processor PEi in advance and executed under the control of the instruction processing unit 1a.
Alternatively, it is stored as a program in the memory 51 in advance,
It may be sequentially read and executed under the control of the sequencer 50.

In the above-described embodiment, the parallelism mode of the multiprocessor system 1 is set in advance as fixed data in each processor PEi, but the parallelism mode may be variably set. That is, each processor PEi sets the parallelism mode to a value that lowers the current parallelism when the address given or generated during execution exceeds the address space of the memory accessible by itself. It becomes possible to read the data stored at the desired address from the memory. As a result, the user can perform programming without being aware of the degree of parallelism of the multiprocessor system 1.

Now, the multiprocessor system 1 is shown in FIG.
As shown in (a), the degree of parallelism is 8, that is, the degree of parallelism mo.
Assume that de = 0. Also, the processor PEi
Of the local memory 3i in the main memory 1b.
It is assumed that the size S of the memory space is stored in advance as data.

The sequencer 50 decodes the address data add obtained by decoding the program stored in the memory 51.
r is input via data bus 10 to all processors P
Give to Ei all at once.

Each arithmetic unit 1i of the processor PEi inputs the supplied address data addr, and accordingly executes the process of step ST20 of FIG. In the processing of step ST20, the instruction processing device 1
a temporarily stores the given address data addr in the register group 1d, and at the same time, the main memory 1
The size S of the local memory space is read from b, and (addr
≧ S) is determined. At this time, when it is determined that this logical expression is not satisfied, that is, the given address data addr specifies the memory space of its own local memory 3i, the process proceeds to the next step ST21, and the instruction processing device 1a Value 0 in the parallel degree mode of the main memory 1b
Is set and the process ends. As a result, the parallelism of the multiprocessor system 1 is maintained at 8 and each of the processors PEi is given the address data addr.
Based on the address, desired data can be read and written in the local memory 3i of its own.

Returning to the processing of step ST20, the instruction processing device 1a determines that (addr ≧ S) is satisfied, that is, the given address data addr exceeds the size of the memory space of its own local memory 3i. If it is determined that it is present, the process proceeds to the next step ST22.

In the processing of step ST22, the instruction processing device 1a sets the value 1 in the data mode of the main memory device 1b, and reduces the parallel degree of the multiprocessor system 1 to 4. As a result, the system configuration shown in FIGS. 1A and 1B is obtained, and the processor PEi having the even processor number pe is locally connected to the processor PEi having the adjacent odd processor number pe. By accessing the memory 3i as its own memory space, desired data can be read / written using the supplied address data addr.

As described in this embodiment, the multiprocessor system 1 has 2 ⁿ (= N) processors, so that the degree of parallelism is reduced to N / 2 or N / 4. Even in such a case, since the symmetry of the system configuration is maintained, control can be performed efficiently.

[0079]

As described above, according to the present invention, the signal deriving means derives the bus switching signal based on the parallelism data and the specific data for uniquely specifying the processor,
The bus selection means operates to connect one of the second and third buses to the first bus based on the derived bus switching signal. The second bus is the first due to the parallelism data
When connected to the bus, the storage means of the processor is set to be accessible by the arithmetic means of the same processor, and conversely, when the third bus is connected to the first bus, the storage means of the processor Is set to be accessible by the computing means of other processors except the processor via the bus switching means of the adjacent processor. Therefore, in the multiprocessor system according to the present invention, it is possible to dynamically rearrange the storage means that each processor independently accesses, without increasing the number of program steps, simply by variably setting the parallel degree data. The effect is that

The above-mentioned effect is that, although the system configuration is fixed, each processor accesses the storage means of another processor via the bus connection-switched by the bus switching means without data transfer between the processors. This makes it possible to arbitrarily and flexibly set the address space of the local memory accessible to each processor.

Furthermore, the above-described effects bring about an effect that the processing speed and processing capacity of each processor, and by extension, the multiprocessor system itself can be improved.

[Brief description of drawings]

1A to 1C are system configuration diagrams for explaining an outline of a multiprocessor system according to a first embodiment of the present invention.

2A and 2B are schematic block diagrams of a processor constituting a multiprocessor system according to an embodiment of the present invention.

FIG. 3 is a schematic diagram for explaining a connection state of input / output buses regarding a memory management unit according to an embodiment of the present invention.

4A and 4B are block diagrams of the memory management unit shown in FIG.

FIG. 5 is a flowchart showing a connection bus selecting operation in the memory management unit according to the embodiment of the present invention.

6A and 6B are schematic diagrams showing a bus connection state in the memory management unit obtained according to the operation flow of FIG. 5;

FIG. 7 is a schematic diagram showing a bus connection state in the case of a parallel degree of 2 obtained according to the operation flow of FIG.

FIG. 8 is a flowchart showing a memory select operation according to an embodiment of the present invention.

9 is a schematic diagram showing an example of a memory select state in the case of a parallel degree of 2 obtained according to the operation flow of FIG.

FIG. 10 is a schematic diagram for explaining a state in which only a data bus is connected and switched in a memory management unit according to an exemplary embodiment of the present invention.

FIG. 11 is a flowchart showing a variable parallel degree setting operation of the multiprocessor system according to the exemplary embodiment of the present invention.

FIG. 12 is a schematic configuration diagram of a conventional multiplexer system in which a plurality of processors are connected in parallel.

13 is a schematic configuration diagram of the processor shown in FIG.

[Explanation of Codes] 1 multiprocessor system PEi processor (computing element) 1i arithmetic unit 2i memory management unit 3i local memory 10 input data bus 20 output data bus 40 local memory bus 50 sequencer 51 memory 80 internal data bus CH bus switching signal MS memory select signal pe processor number mode parallel degree Addr3 upper 3 bits of address S size of local memory space (i = 0, 1, 2, ..., 7) In each drawing, the same reference numerals denote the same or corresponding portions. Show.

Claims (1)

[Claims] 1. A multiprocessor system having at least two processors connected in parallel via the same bus, each processor performing processing in parallel, wherein each processor is connected to the same bus. A first arithmetic operation means, a storage means, a bus switching means, and the storage means and the bus switching means of one of the adjacent processors are connected via the bus switching means.
Bus, a second bus connecting the arithmetic means and the bus switching means, a bus switching means, and a third bus connecting the bus switching means of the other adjacent processor. The arithmetic means further includes signal derivation means for deriving a bus switching signal based on specific data and parallelism data uniquely identifying the processor, which are stored inside beforehand, and the bus switching means further includes: Based on the switching signal derived by the signal deriving means, the second and third
A multiprocessor which comprises bus selecting means for selecting any one of the buses and connecting it to the first bus, wherein the parallelism data is data for specifying the number of the processors for accessing the storage means in parallel. system.