JPS6126699B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microcomputer system, and in particular, it has a plurality of memory banks in the same memory space (address space) of a CPU, and a DMA controller (direct memory access controller) in addition to the CPU. ) with the above
The present invention provides a bank switching device in a system where memory bank selection is performed by a CPU or a DMA controller.

The present invention applies to the above system.
The configuration allows each channel of the CPU and DMA controller to select a memory bank individually,
Even when the CPU (or DMA controller) is selecting a memory bank, the DMA controller (or CPU) can independently select a memory bank.In other words, each channel of the CPU and DMA controller can select a memory bank in multiple ways. It is made so that you can choose.

In recent microcomputer systems, this system is expanding, and memory expansion is also required accordingly.

For example, a CPU (Z-80) or DMA controller equipped with a 16-bit address bus from _A0 to _A15 can directly access a memory space of up to 64K bytes. However, if this memory configuration is further expanded to include 32K bytes of memory (bank 2) in addition to the 64K bytes of memory (bank 1), the total memory capacity will be 96K bytes, and this CPU will This will exceed its maximum memory space (64K bytes).

This causes the CPU or DMA controller to
In order to read/write data to the 64 Kbyte memory bank 1 and the 32 Kbyte memory bank 2, it was necessary to select the memory bank 1 and the memory bank 2 by appropriately switching control.

Here, a general memory bank switching configuration by the CPU or DMA controller is shown in Fig. 1. In Fig. 1A, 64K
Same as Byte's memory bank 1 (BK1)
A 64K byte memory bank 2 (BK2) is provided, and the CPU or DMA controller controls banks 1 and 2 for each bank's entire memory space (shaded area).
An example is shown in which the two can be mutually switched. In this case, memory banks 1 and 2 contain the operating system, which is the basic control program for the system.
It is necessary to prepare each OS.

In addition, in FIG. 1B, the operating system OS is not provided in banks 1 and 2, but the memory bank 1 (BK
1) Configure the front memory space (capacity of 32K bytes) and store the operating system OS here
When memory bank 1 (BK1) is selected, the front memory space and rear memory space correspond, and when memory bank 2 (BK2) is selected, the front memory space and memory space correspond, and the CPU or DMA A controller switches between banks 1 and 2. This makes it possible to use memory more effectively than in FIG. 1A.

However, in both the memory bank switching configurations shown in FIG. 1A and B, the CPU and DMA
For example, the controller's memory bank selection is
If the CPU is executing a program in memory bank 1, the program execution of the CPU must be finished.
Select operation by the DMA controller is not possible, and the DMA controller also selects memory bank 1.
When processing is in progress, the CPU cannot perform a select operation until the processing of the DMA controller is completed, resulting in a very inefficient system.

The present invention has been proposed to solve the problems of the conventional system, and FIG. 2 shows a conceptual diagram of the operation of the memory bank switching state according to the present invention.

FIG. 2A shows the memory bank switching operation for the CPU. For the CPU, when bank 1 is selected, the front memory space and rear memory space correspond to each other, and when bank 2 is selected, the front memory space and bank 2 correspond to each other. The side memory space corresponds. FIG. 2 shows the memory bank switching operation by the DMA controller. For the DMA controller, selecting bank 1 corresponds to the entire area (front, rear memory space, etc.), and selecting bank 2 corresponds to the entire area (front, rear memory space, etc.). The front and rear memory spaces, ) correspond to each other.

Then, you can perform the select operation as described above.
The CPU and DMA controller are designed to be able to perform memory bank selection operations independently, and therefore, Figure 2C is able to obtain the selection state of the CPU and DMA controller as shown in Figure 2D. can. In this second figure, the diagonal line at the top right is
The CPU select area, and the diagonal line at the top left indicates the DMA controller select area.

That is, in the present invention, each channel of the CPU and DMA controller is configured to be able to perform bank selection independently, and as shown in FIG.
The DMA controller can select bank 2 while the DMA controller has bank 1 selected, and conversely, the DMA controller can freely select banks of other DMA channels and the CPU even while DMA is being executed. be.

A control configuration for this purpose is shown in FIG. 3, and FIG. 3 will be explained below.

In this figure, the DMA controller has two channels and the memory bank is memory bank 1.
An example including memory bank 2 (BK1) and memory bank 2 (BK2) is shown.

The flip-flop _F1 holds the bank select state of the CPU, and is set and reset by the bank select instruction signal C1. When _F1 is reset, memory bank 1 is selected, and when it is set, memory bank 2 is selected.

That is, the set output of _F1 , the signal AB15 indicating the distinction between the front memory space and the rear memory space of the memory bank, and a signal that becomes "H" level when data is not being transferred by the DMA controller are input to the NAND gate G1. has been done.

Flip-flop _F2 holds the bank select state of channel 1 of the DMA controller, and is set and reset by a bank select instruction signal C2 from the DMA controller. Applicable
Memory bank 1 is selected when _F2 is reset, and memory bank 2 is selected when F2 is set.

Flip-flop _F3 holds the bank select state of channel 2 of the DMA controller, and is set by bank select instruction signal C3.
Memory bank 1 is reset and reset
is also set and memory bank 2 is selected.

The set output of _F2 is a signal DACK indicating whether data is being transferred on channel 1 of the DMA controller.
1 (“H” level during data transfer) and is input to the AND gate G2. Similarly, the set output of _F3 is input to AND gate G3 together with signal DACK2 as described above for channel 2 of the DMA controller. These and gate G2
The gate outputs of and G3 are input to one side of another NOR gate G5 via a NOR gate G4.
The other input of the NOR gate G5 is the gate output of the above-mentioned NAND gate G1.

Then, the output of the NOR gate G5 is directly used as the select signal SELB2 of the memory bank 2 (BK2).
In addition, the signal passed through the inverter I is used as the select signal SELB1 for memory bank 1 (BK1). The select signal SELB1 is sent to the memory bank unit via an AND gate G6 to which the memory read/write control signal R/W is input.
The select signal SELB2 is also introduced into the memory bank unit BK2 via an AND gate G7 to which the memory read/write control signal R/W is input.

Therefore, if the flip-flop _F1 is held in the reset state by, for example, the bank select instruction signal C1 of the CPU, the output Q1 will go to the "L" level and the output of the NAND gate G1 will go to the "H" level. At this time, assuming that the DMA controller side is not performing data transfer, DACK1 and
When DACK2 is at "L" level, the output of NOR gate G4 is held at "H" level. Therefore, the output of the NAND gate G1 (H level) due to the reset of the flip-flop _F1 causes the output of the NOR gate G5 to go to the "L" level, and the select signal SELB1 is outputted via the inverter I to select the memory bank BK1.

Also, in the above state, the flip-flop _F1 is set and the rear memory space selection instruction signal AB15 is set.
Even if it is set to "H" level, the output of NAND gate G1 is "L" from the "H" level.
level. Therefore, the output of NAND gate G5 becomes "H" level and is selected. That is,
The CPU selection state shown in FIG. 2A is obtained. In this case, the selection of memory bank BK2 by the CPU is based on the memory bank BK2 instruction (setting of flip-flop _F1 ) and this memory bank BK2.
address instruction for the rear memory space (selection instruction signal
AB15 is at "H" level), and when selecting the memory bank BK2, simply setting the address instruction for this front memory space, that is, the selection instruction signal AB15 to "L" level, selects the memory bank BK1. You can switch back to select. This means that the CPU is in memory bank BK1
To enable bank switching operations when referring to data in memory bank BK2 and continuing the program again during execution of a program in the front memory space of the memory bank to be easily performed using only the address instruction (instruction signal of AB15). It is.

On the other hand, for the bank select operation on the DMA controller side, the current bank select instruction signal C2
Assume that flip-flop _F2 of channel 1 is held in the reset state by . In this case
DACK1 becomes “H” level and DACK2 goes “L”
Since the output Q2 of _F2 is at the "L" level, the output of the AND gate G2 is at the "L" level, and the AND gate G3 is also at the "L" level.

At this time, the signal on the CPU side is at "L" level, so the output of NAND gate G1 is "H".
held at the level.

Therefore, the output of NOR gate G4 becomes "H" level, the inputs of NOR gate G5 are both "H" level, and the output of NOR gate G5 becomes "L" level. Therefore, the memory bank BK1 to which the select signal SELB1 is output via the inverter I is selected.

Further, when flip-flop _F2 is set in the above state, the output of AND gate G2 becomes "H" level, the output of NOR gate G4 becomes "L" level, and the output of NOR gate G5 becomes "H" level. Therefore, SELB2 is output and memory bank BK2 is selected.

This operation is the same for channel 2,
The selected state of the DMA controller shown in FIG. 2B is obtained.

Now, when the CPU sets flip-flop _F1 and selects memory bank 2 (BK2) to execute a processing operation, channel 1 of the DMA controller selects memory bank 1 (BK1) and stores data. When you want to read,
A hold signal is output from the DMA controller to the CPU, and DACK1 is set to "H" level. At this time, the signal and DACK2 become "L" level.

Then, both inputs of NOR gate G5 become "H" level and select memory bank 1 (BK1). Similarly, CPU is memory bank 1
Even when (BK1) is selected and a processing operation is being executed, the other memory bank 2 (BK2) can be selected and switched by the DMA controller.

This operation is similar to the CPU shown in Figure 2 C and D.
This is the selected state of the DMA controller and the CPU
Each channel of the DMA controller can independently select a memory bank. In other words, while the CPU selects memory bank 1 and executes a program, etc., when data in memory bank 2 is needed, the DMA controller selects memory bank 2 and switches.
After reading the necessary data, the CPU can be used again.

Therefore, the device of the present invention is characterized in that the memory banks are efficiently switched by each channel of the CPU and the DMA controller, resulting in very high system efficiency.

[Brief explanation of the drawing]

1A and 1B are conceptual diagrams showing the memory bank switching states of the conventional system; FIGS. 2A, B, C, and D are conceptual diagrams showing the switching states of the memory banks of the system of the present invention; and FIG. FIG. 3 is a diagram showing a control circuit configuration according to the present invention. BK1 and BK2: memory bank, _F1 to _F3 : flip-flop F, G1: NAND gate, G2 and G3: AND gate, G4 and G5: NOR gate.

Claims (1)

[Claims] 1. A plurality of memory banks BK1 and BK2 are provided corresponding to the maximum memory space of the CPU and the DMA controller, and one memory bank BK1 is divided into front and rear memory spaces in terms of addresses. In the microcomputer system, which constitutes a common area portion including a switching system, and in which the selection and switching of the memory banks BK1 and BK2 can be performed by the CPU and the DMA controller, be arranged and correspond to it.
A holding means for holding a state of a memory bank selection instruction from each channel of a CPU or a DMA controller, and a circuit means for outputting a memory bank selection signal based on the selection instruction set in the holding means, further comprising: When there is a select instruction for the memory bank BK2 from the CPU, the circuit means generates a select signal for the memory bank BK2 only under the condition of an address instruction for the rear memory space which is divided into front and rear memory spaces in terms of addresses of the memory bank BK2. At the same time, when the bank BK2 is selected, memory bank BK is output in response to an address instruction of the front memory space.
A memory bank switching device in a microcomputer system configured to switch to a select signal of No. 1.