JPH01226052A - Memory controller - Google Patents

Abstract

PURPOSE:To access other divided space data during the execution of a program in a bank ROM space by providing 1st and 2nd address registers so that two divided areas can be accessed. CONSTITUTION:In case of directly specifying only a fixed address space in a ROM 26 by normal access, a selector 23 is controlled so as to select address data in an address bus 22 and apply the data to the ROM 26. In case of making access to one divided area in order to read out data simply from the ROM 26, the selector 23 accesses the divided area in accordance with the upper two bits of an address register 27. In case of making access to another divided space on the way of making access to one divided space of the ROM 26, the combination of outputs of the address register 27 and the address bus 22 and the independent output state of the output of an address register 28 are switched by the selector 23.

Description

[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention provides a memory control device that efficiently controls a ROM having a space larger than the range that can be specified by normal address data of a microprocessor. Regarding.

(Prior Art) Advances in semiconductor memory integration technology have made it possible to construct large-scale memories.

This memory capacity is larger than the memory space normally accessible by a microprocessor. For this reason, even if the microprocessor program is stored and used in memory, unused space will be generated.

Therefore, in order to make effective use of unused space.

A control device as shown in FIG. 3 has been conventionally used. That is, the address bus 12 and data bus 13 of the microprocessor 11 are connected to the ROM 14. The address bus 12 is further connected to an address decoder 15 and the data bus 13 is also connected to an address register 16. The decoded output of the address decoder 15 is
It is used as a chip enable signal for the ROM 14, and the output of the address register 16 is used to specify the upper address of the ROM 14 via the selector 17. The selector 17 selects either the upper address from the address bus 12 or the upper address from the address register 16 and supplies it to the ROM 14.

The address spaces that the microprocessor 11 can assume are a fixed address space A and a bank area B, as shown in FIG.

On the other hand, the actual memory space of ROMI 1 consists of a fixed address space All and a divided space A12 . A13. There is A14. and split window Iu
l A 12. A13. Each of A14 has a capacity similar to that of a fixed address space.

The address space of the ROM 14 is the macro processor 1.
Addresses that 1 can normally specify directly are within the fixed address space All. If accessing only this fixed address space All is sufficient, the address bus 12
The lower address of the fixed address space All is specified through the selector 17, and the upper address is specified through the selector 17. Data from ROM 14 is read by microprocessor 11 via data bus 13.

The ROM 14 further includes a plurality of divided spaces A12 . A13. Al1, which has a larger capacity than the direct addressing capacity of the microprocessor 11.

Therefore, these divided spaces A12. A13. Al1
When accessing the address register 16, the address decoder 15 switches the selector 17, causing the selector 17 to select the output of the address register 16. Then, the upper two bits of the address are given to the address register 16 via the data bus 13. As a result, the address data from the address bus 12 specifies a lower address in the ROM 14 space, and the output of the address register 16 specifies an upper address. The output of the address register 16 is divided into divided spaces A12, . A13. In addition to specifying one of Al1, the upper address is also specified.

(Problems to be Solved by the Invention) The conventional memory control device described above can obtain the above-described control when data in a divided space is required while reading program data in a fixed address space of the ROM 14.

However, the conventional device is limited to the function of accessing one of the divided spaces and reading necessary data while accessing the fixed address space of the ROM 14 to read and execute program data. If this function is limited, for example, if program data is stored in one partitioned space and data necessary for program execution is stored in another partitioned space, memory access becomes complicated. Become. In other words, when switching between a fixed address space and one divided space, it is sufficient to control whether or not the output of the address register is output via the selector, but when switching between a divided space and another divided space, In this case, the data in the address register 16 must be saved once and the upper address of the other divided space must be sent each time, resulting in poor access efficiency.

Therefore, the present invention proposes an RO which has more space than can be directly addressed by a microprocessor.
It is an object of the present invention to provide a memory control device in which the degree of freedom of control is expanded and access efficiency is high when performing address control on M.

[Structure of the Invention] (Means for Solving the Problems) The present invention provides a fixed address space that can be directly designated by address data from a microprocessor, and a plurality of spaces having the same capacity as the address space in addition to this address space. When accessing a ROM having a divided space, the following means are provided.

That is, 1st. The data bus of the microprocessor is connected to the second address register, and the first address register is connected to the selector. The configuration is such that the output of the second address register and the address bus output of the microprocessor are input. This selector selects three states: an individual output state of the address bus output, a combination output state of the address bus output and the output of the first address register, and an individual output state of the second address register output. It can be taken as a target. This state is controlled by the address decoder, which is supplied with input/output commands and address data from the microprocessor, and based on this input information, when there is an input/output command, the second address register output is in a single output state. and when there is no input/output command, the selector is controlled to output only the address bus output, or the address bus output and the first The selector is controlled to an output state in combination with the address register output.

(Function) With the above means, the present invention can provide addresses that can access the two divided areas by providing the first and second address registers.

By using the input/output command of the microprocessor, it is possible to recognize which divided area is to be accessed, whether it is a program data request or a normal data request, so that the access area can be easily switched.

(Example) Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows one embodiment of the present invention, in which an address bus 22 of a microprocessor 21 is connected to a selector 23 and an address decoder 24. In FIG.

Further, a data bus 25 is connected between the microprocessor 21 and the ROM 26, and this data bus 25 is connected to the first . Also connected to the second address register 27.28. Further, input/output instructions Xi of the microprocessor 21 are supplied to an address decoder 24. The address decoder 24 receives a chip enable signal
2 and outputs a 2-bit selector control signal
Outputs 3. Chip enable signal X2 is ROM2
6 is in the chip selection state, or other ROMs are put in the control state.

The selector 23 includes first and second address registers 27.
．． 28 and address data from the address bus 22 are supplied.

Here, the selector 23 selects the address data from the address bus 22 alone, or combines the address data from the address bus 22 and the output of the first address register 27, depending on the contents of the selector control signal X3. The selected state or the second address register 28
It is possible to take three states in which the output of is selected independently.

The address data selected and derived by the selector 23 is
It is supplied to the addressing section of M26.

This embodiment is configured as described above.

(1) When only the fixed address space of the ROM 26 is directly designated by normal access, the selector control signal X3 controls the selector 23 to select address data on the address bus 22 and provide it to the ROM 26. The selector control signal X3 is "00" at this time, because the input/output command X1 is, for example, "Oa".

(2) Next, when accessing one divided area to simply read data from the ROM 26, the input/output command is "10" or 01" or '
11''. At this time, the output of the selector 23 is divided into divided areas A12 . A13. A1
Access 4. Further, at this time, the selector control signal X3 is the output of the first register 27,
The upper address of the ROM 26 is specified, and the output from the address bus 22 is used for the lower address.

(3) Next, when accessing another divided space while accessing one divided space of the ROM 26,
The selector 23 switches between a combined output state of the address 27 and the output of the address bus 22 and a single output state of the output of the address register 28. In other words, as shown in the truth table shown in FIG.
”, the output of the second register 28 is selected.

As described above, this embodiment uses input/output commands, and the first . By providing the second register, even if an irregular request to access another divided space occurs while a program in the divided space is being executed, the access can be realized at high speed.

[Effects of the Invention] As explained above, according to the present invention, even while a program in the bank ROM space is being executed, data in other divided spaces can be accessed, and ROMs with increasingly large capacities can be used. In addition, by using input/output instructions, memory control can be performed with a simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of the present invention, FIG. 2 is an operation explanatory diagram shown to explain the operation of the circuit in FIG. 1,
FIG. 3 is a circuit diagram showing a conventional memory control device, and FIG. 4 is an explanatory diagram of an address space between a microprocessor and a ROM. 21...Microprocessor, 22...Address bus, 23...Selector, 24...Address decoder, 25...Data bus, 26...ROM, 27.2
8...1st. Second address register. Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

[Scope of Claims] A ROM having a fixed address space that can be directly designated by address data from a microprocessor, and a plurality of divided spaces having the same capacity as the address space in addition to this address space; The first to which the data bus is connected
, a second address register, and the outputs of the first and second address registers and the address bus output of the microprocessor are input, and the single output state of the address bus output, the address bus output and the first address a selector that can selectively take one of three states: a combination output state with the output of the register, and an independent output state of the second address register output; Based on the information, when there is an input/output command, the selector is controlled to output the second address register output alone, and when there is no input/output command, the selector is controlled to output the address bus output independently according to the contents of the address data. A memory control device comprising: an address decoder that controls the selector to a state, or controls the selector to a combination output state of the address bus output and the first address register output.