JPS6230660B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data processing device including a microprocessor, and more particularly to a data processing device having a memory capacity larger than the memory address space that can be directly accessed by the microprocessor.

Currently, most data processing devices including microprocessors use semiconductor memory, and this memory is accessed and used by the CPU address output by the microprocessor (set by the address output bits of the processor). There is.
On the other hand, in microprocessor hardware,
There is an upper limit to the amount of memory that can be directly addressed by a CPU address. For example, if the processor has a 16-bit address terminal, it is possible to specify addresses of 64 kilobytes.
In addition, recently, due to the reduction in the cost of semiconductor memory, the increased processing power required of data processing devices including microprocessors, and improvements in software technology, the original upper limit memory capacity of microprocessors has been exceeded. There is a need for data processing devices that require large amounts of memory.

Conventionally, in data processing devices that require memory in a system that exceeds the upper limit memory capacity of a microprocessor, the memory is divided into multiple chips (hereinafter referred to as memory banks).
The method used was to select any memory bank among these, as long as the address space of the microprocessor allowed it, and connect it to the microprocessor for use.

As such a data processing device, a configuration as shown in FIG. 1 is known. The data bus 2 of the microprocessor 1 has a program memory 4, a memory selection port 5, and memory banks 7, 8, 9, 10.
are connected to each other. Further, the address bus 3 is connected to a program memory 4, an address decoder 6, and memory banks 7, 8, 9, and 10, respectively.

FIG. 2 is a memory address map for the system of FIG. Here, the capacity of the address space of the microprocessor is assumed to be 64 kilobytes. The program memory 4 exclusively occupies the address space of the microprocessor 1 from addresses 0000 to BFFF. Therefore, the space from addresses C000 to FFFF becomes the address space given to memory banks 7, 8, 9, and 10. Microprocessor 1 writes selection data for selecting one of memory banks 7, 8, 9, and 10 to memory selection port 5 using write control signal 12. The written selection data becomes a selection control signal 14 and is input to the chip select gate 11. On the other hand, the address decoder 6 decodes the address space given to the memory bank at any time, and the address decode signal 15 is activated only when the address of the microprocessor 1 points to the space from C000 to FFFF. As a result, the chip select of only one selected memory bank becomes active, and the microprocessor 1 can access the memory. Therefore, since the program memory 4 and the memory banks cannot be located in the same address space, there is a drawback that the capacity of each memory bank is limited accordingly. Furthermore, if the program or data to be accessed spans multiple memory banks, for example, the program or data stored in the memory bank may span from the second half address of memory bank 7 to the first half address of memory bank 8. In such a case, there is also the drawback that memory banks must be switched in a complicated manner at the boundary in order to refer to data.

SUMMARY OF THE INVENTION The present invention aims to improve the above-mentioned drawbacks, and aims to provide a data processing device in which a part or all of the address space of a program memory is shared with the address space of another memory.

Another object of the present invention is to provide a data processing device that uses a shared address to access a memory capacity that is greater than the capacity that can be accessed by the address.

In a data processing device having a microprocessor and first and second memories, a part of the address space that can be specified by the microprocessor is allocated to the first memory, and the remaining address space is allocated to an integral multiple of the address space. allocating space in said second memory, said first memory being supplied with addresses directly from said microprocessor, and said second memory being supplied with addresses in said remaining address space in a preset off state; a first mode in which an address qualified with a set address is provided; and a second mode in which access to the first memory is prohibited and all of the address space that can be specified by the microprocessor is allocated to the second memory. The feature is that the mode can be selectively executed.

An embodiment of the present invention will be described in detail below based on the drawings.

FIG. 3 is a functional block diagram showing one embodiment of the present invention. Data bus 110 from microprocessor 100 is connected to program memory 140, offset address register 190, and memory block 150, respectively. address bus 1
20 is connected to a program memory 140, an address decoder 180, an address modification circuit 200, and an address multiplexer 210. A program memory inhibit flip-flop 160 is connected to the program memory 140 to inhibit access thereto. FIG. 4 shows the memory map during normal operation. During normal operation, the program memory inhibit flip-flop 160 is reset, and the program memory is set from 0000 to
Occupies BFFF address space. on the other hand,
The address space C000 to FFFF is an address space given to the memory block 150, but its capacity is smaller than the total capacity of the memory block 150. Address decoder 180 decodes the above address (C000-FFFF) and activates chip select signal 240 only when the microprocessor selects the above address according to memory selection signal 240. Microprocessor 100 outputs the desired offset address data to offset address register 190. Offset address data is input to address modification circuit 200 by offset address bus 250. On the other hand, the CPU address is input to the address modification circuit 200, and address modification (for example, addition) is performed here. The modified address signal is input to memory address multiplexer 210 as effective address signal 260. Memory address multiplexer 210 is controlled by multiplexer control flip-flop 170, and the B side input is selected during normal operation. As a result, memory block 150 is addressed by an effective address modified by the offset address. Memory block 15
Consecutive physical addresses are assigned to 0, and the microprocessor 100 stores the offset address data in the offset address register 19.
By setting it to 0, the range in which the above effective address can change (CPU address is C000 to FFFF
The memory blocks within the range that can change when the data changes to (the range that can change when the data changes) are selected as one memory bank.

Next, the operation in the memory block selection mode will be explained. In the memory block selection mode, a program memory inhibit flip-flop is set and all accesses to program memory 140 are inhibited. Also multiplexer controlled flip-flop 1
70 is also set, and memory address multiplexer 210 selects the A side input. Further, the address decoder 180 is opened by the output of the program memory inhibit flip-flop, and the memory block 150 is selected even in the space from addresses 0000 to BFFF, which was inhibited in the normal mode. On the other hand, the address signal input to the memory block 150 is a CPU address, and it is better not to modify it with offset address data. Also, although it may be done, addresses can be used more effectively if it is not done. The memory map in this mode is shown in FIG. In this mode, all memory blocks 150 are connected to the microprocessor 1.
00, and the microprocessor can execute programs in memory block 150 or refer to data without rewriting offset address data to switch memory banks.
It is also possible to switch between the normal mode and the memory block selection mode using a program.

According to this embodiment, it is not only possible to select a series of areas as one memory bank using an arbitrary address in a memory block as a starting address, but also to select multiple or all memory banks at the same time by switching the mode. This has the effect of making selection possible.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a conventional data processing device. FIG. 2 is a memory address map diagram of a conventional data processing device. FIG. 3 is a functional block diagram showing one embodiment of the present invention. FIGS. 4 and 5 are memory address map diagrams in one embodiment of the present invention. 1,100...Microprocessor, 2,11
0...Data bus, 3,120...Address bus, 4,140...Program memory, 5...Memory selection port, 6,180...Address decoder, 7,8,9,10,150...Memory block , 11... Chip select gate, 12, 13
0... Control signal, 13,220... Chip select signal, 14... Selection control signal, 15,240...
...Decode signal, 160...Program memory inhibit flip-flop, 170...Multiplexer control flip-flop, 190...Offset address register, 200...Address modification circuit,
210...Memory address multiplexer, 23
0... Multiplexer control signal, 250... Offset address, 260... Effective address, 27
0...Memory address.

Claims (1)

[Claims] 1. In a data processing device having a microprocessor and first and second memories, a part of the address space that can be specified by the microprocessor is allocated to the first memory, and the remaining address space is an integral multiple thereof. space in the second memory, the first memory is supplied with addresses directly from the microprocessor, and the second memory is preset with addresses in the remaining address space. a first mode in which an address modified with an offset address is provided; and a second mode in which access to the first memory is prohibited and all of the address space that can be specified by the microprocessor is allocated to the second memory. A data processing device characterized in that it is capable of selectively executing the second mode.