JPS60189561A - Memory access control system - Google Patents

Abstract

PURPOSE:To omit a ROM and to cope with the change or the like of a system constitution efficiently by storing information for initial program loading in a readable/writable memory. CONSTITUTION:When the rising operation of a sub-processor 11 side is to be executed by a main processor 10 side, the main processor 10 sets up an address conversion circuit 14 and a selection circuit 15 and then sends a start signal to the bus-processor 11 through a register 16 and the sub-processor 11 starts its reading operation from X'0000'. The information of X'0000' on an address bus 23 is converted at its address into address information actually accessing a common memory 12 by the address conversion circuit 14. Since common memory access mode information is set up in the selection circuit 15 and the X'0000' is included in a prescribed address range, a selection line 29 is turned on and the common memory 12 is turned to a selecting state when the memory is accessed from the sub-processor 11. Data are inputted through a bus 22, a try state circuit 19 and a bus 24.

Description

DETAILED DESCRIPTION OF THE INVENTION (A) Technical field of the invention The present invention involves both a main processor and a sub-processor, in which the main processor is provided with a labor memory, the sub-processor is provided with a local memory,
The present invention also relates to a memory control method in a data processing system in which a common memory is configured such that it can be accessed by both a main processor and a sub-processor.

(b) Conventional technology and problems In recent years, microprocessors have become widespread and cheap;
For reasons such as ease of use, data processing systems are often constructed by combining a plurality of microprocessors (7).

FIG. 1 shows an example of the configuration of such a data processing system. In the figure, 1 is a main processor consisting of a microprocessor, 2 is a sub-processor also consisting of a microprocessor, 3 is a common memory, 4 is a local memory, and 5 is a main processor consisting of a microprocessor. 6 is a read-only memory (ROM), 6 is a selection circuit, 7 is a driver circuit, and 8.9 is a common bus. In the first factor, only one sub-processor is shown, but depending on the system configuration, there are cases where multiple sub-processors are provided.

In the figure, the local memory 4 is used only by the sub-processor 2 side, and is not used by the main processor 1 side. On the other hand, the common memory 3 is used by both the main processor 1 side and the sub processor 2 side. When the common memory 3 is used from the sub-processor side, access is performed via the DMA circuit 7. Needless to say, various I10 devices are connected to the common buses 8 and 9, respectively (not shown in the figure).

Here, the ROM 5 stores a program for IPL (initial program loading) in a fixed manner, and when starting up the system on the sub-processor 2 side, the ROM 5 is first set to a selected state by the selection circuit 6, and the sub-processor 2 is set to a selected state. The startup operation is performed by the processor 2 accessing the ROM 5.

In this way, the ROM' used for IPL is generally used in microprocessors where the startup address is fixed (
For example, x'oooo'), it is appropriate to use a read-only memory.

However, in this way ROM'a? When used, it is not easy to change or modify the program after system configuration, resulting in a problem of lack of flexibility.

(c) Purpose of the Invention The purpose of the present invention is to solve the above-mentioned problems and increase the flexibility of the system configuration by eliminating the ROM on the sub-processor side and configuring it entirely with readable/writable memory. shall be.

B) Structure of the Invention In order to achieve the above object, the present invention has a main processor and a common memory connected on a first common bus, a sub-processor and a local memory connected on a second common bus, and The memory is accessed from both the main processor and the sub-processor.In the above-mentioned main processor and the sub-processor, the memory access by the sub-processor is in the access mode to the common memory. memory selection means that holds access mode instruction information for instructing whether the local memory is in an access mode, has an address information determination function, and sends a memory selection signal to any of the memories to be accessed; an address conversion means for converting memory address information sent from the sub-processor to memory address information on the common memory; the memo IJ'7 access from the sub-processor is in the access mode to the common memory; When the address information is within a predetermined range, the address information sent from the processor is converted by the address conversion means and sent to the common memory, and a selection signal is sent from the selection means to the common memory. I'll take a look at what I did.

(e) Embodiment of the Invention FIG. 2 is a book diagram of a data processing device according to an embodiment of the invention, in which 1o is a main processor consisting of a microprocessor, and 11 is a main processor of the same 12 is a common memory, 13 is a local memory, 14 is an address conversion circuit, 15 is a selection circuit, 16 is a 1-bit register, 17.18 is an AND circuit, 19.20 is a tri-state circuit, and 21 is a An address bus on the main processor side, 22 a data bus on the main processor side, 23 an address bus on the sub processor side,
24 is a data bus on the sub-processor side, 25 is a read control line from the sub-processor 11, 26 is a write control line from the sub-processor 11, 27 is a start signal line, 28 is a selection signal line to the local memory 13, 29 is a Common memory 1
This is a selection signal line to 2.

In the figure, the address conversion circuit 14 is a circuit that converts an address based on address conversion control information set in the address conversion circuit on the address bus 23 and sends it onto the address bus 21. Also, based on the value of response information,
This circuit turns on either the selection signal line 28 or 29 when there is a memory access from the sub-processor 11, and selects either the local memory IJ 13 or the common memory 12.

Further, the selection signal line 29 controls AND circuits 17 and 18, turns on the tri-state circuit 19 when reading from the common memory 12 from the sub-processor 11, and turns on the tri-state circuit 19 when writing from the sub-processor 11 to the common memory 12. Turn on circuit 20.

The operation of the embodiment will be explained below. When the main processor side starts up the sub-processor side, first,
The main processor 10 sets common memory access mode information t in an access mode instruction flag information holding register (not shown) in the selection circuit 15. Further, the main processor 10 sets address translation control information t in an address translation control information holding register (not shown) in the address translation circuit 14. This address translation control information is space information.

In this way, the address conversion circuit 141 selection circuit 15
After making the settings, the main processor 10 sends an activation signal to the sub-processor +)'11 via the register 16. As a result, the sub-processor 11 performs x' o
The read operation starts from address ooo'. The x'oooo' address information on the address bus 23 is converted into an address in the address conversion circuits 1 and 4, and is actually stored in the common memory 1.
This is the address information for accessing 2.

In addition, common memory access mode information is set in the selection circuit 15, and the address x'oooo' is within a predetermined address range, so for memory access from the sub-processor 11, the selection signal line is turned on, and the common memory 12 is placed in a selected state. Specifically, the signal on the selection signal line 29 is the memory chip enable (CE
) signals, the data read from the common memory 12 is transferred to the data bus 22 . Tri-state circuit 19. Through the data bus 21', the subprocessor li
be taken in.

FIG. 3 is a diagram showing the relationship X between the address map on the main processor side and the address map on the sub processor side.
In the figure, 30 is the address map of the main processor side, 3
1 is an address map on the subprocessor side, a is a common memory address in the common memory startup mode, and b is a local memory address in the common memory startup mode. The address conversion shown in FIG. 3 is performed by the address conversion circuit 14 shown in FIG. There is.

Note that in common startup mode, subprocessor 2
An access to the address x'oooo'Kouji~X'7FFF' from ``X'' is performed to the common memory 3 after the address is converted, but an access to the FFFF' address in the same mode is directly accessed to the local memory 3. This is done for memory 4.

Furthermore, in local memory startup mode, which is another mode, x' oo from subprocessor 2
Accesses to addresses oo' to X'7FFF' are made to the local memory 4, and accesses from subprocessor 2 to addresses X'5ooo' to
Access to the address is performed to the common memory 3 after address translation.

With the above configuration, conventionally, information for IPL stored in the ROM is stored in the common memory 3, and the subprocessor 2 reads this information from the common memory 3. be able to.

(f) Effects of the Invention According to the present invention, the ROM for IPL can be omitted, and the information for IPL can be stored in a readable/writable memory. Able to efficiently deal with changes in system configuration, etc.

Furthermore, by having two access modes, the sub-processor can operate independently regardless of the main processor's operation, allowing the entire system to operate efficiently.

[Brief explanation of the drawing]

FIG. 1 is a configuration example of a conventional data processing system, FIG. 2 is a block diagram of a data processing device according to an embodiment of the present invention, and FIG.
The figure shows the relationship between address maps in the common memory access mode. In FIG. 2, 10 is a main processor, 11 is a sub-processor, 12 is a common memory IJ, 13 is a local memory, 14 is an address conversion circuit, and 15 is a selection circuit. Ai bu I! 1 0 therapy 2nd

Claims (1)

[Scope of Claims] (11 A main processor and a common memory are connected on a first common bus, a sub-processor and a local memory are connected on a second common bus, and the common memory is connected to the main processor and a In a data processing system configured to be accessible from both processors, the subprocessor indicates whether memory access by the subprocessor is in the common memory access mode or the local memory access mode. memory selection means that holds access mode instruction information and has an address information determination function and sends a memory selection signal to any memory to be accessed; and memory address information sent from the subprocessor to the common memory. Equipped with address conversion means for converting into memory address information,
When the subprocessor is in the subprocessor access mode and the memory address information is within a predetermined range, the address information sent from the subprocessor is converted by the address conversion means and sent to the common memory, and from the selection means. A memory access control system characterized in that it is configured to send a selection signal to the common memory. (2) When the main processor starts up the subprocessor, the main processor sends access mode instruction information to the memory selection means, sends address conversion control information to the address conversion means, causes the information to be held, and then, Claims 7 characterized in that the main processor sends an activation signal Z to the sub-processor and has address mode instruction information so that the sub-processor accesses the common memory or the local memory. The memory access control method described in paragraph (1).