JPH0566992A - Data access system for eeprom - Google Patents

Abstract

PURPOSE:To write data in an EEPROM by a CPU without being conscious of physical limit concerning the data write operation of the EEPROM and to improve entrie speed for the processing executed by the CPU by replacing the memory space of the EEPROM with a static RAM. CONSTITUTION:A static RAM 4 is directly connected to the address bus and data bus of a CPU 1. The address bus and data bus of an EEPROM 3 are connected through an EEPROM control part 2 to the respective buses of the CPU 1. Thus, the EEPROM 3 is used for storing data, and the CPU 1 accesses the data on this EEPROM 3. The static RAM 4 stores the completely same data as the data in the EEPROM 3 and can execute write/read from the CPU 1 at all times. Then, the EEPROM control part 2 controls the exchange of the data between the static RAM 4 and the EEPROM 3.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a digital circuit having a CPU, and more particularly to an EEPROM data access method in a circuit using an EEPROM as a storage element.

[0002]

2. Description of the Related Art In a digital circuit having a conventional CPU using an EEPROM as a storage element, the CPU is
The data stored in the EPROM is directly accessed.

[0003]

As described above, the EE
In a conventional digital circuit using a PROM as a storage element, since the CPU directly accesses the data stored in the EEPROM, when writing data to the EEPROM, due to the characteristics of the EEPROM, in terms of byte write, the static RAM has a capacity of 100,000. It takes about twice as long. Therefore, there is a problem that the more the CPU performs the writing process to the EEPROM, the longer the entire processing time becomes.

[0004]

SUMMARY OF THE INVENTION The EEPROM data access method of the present invention is an EEPROM for storing data.
ROM, CPU for accessing data on the EEPROM, static RAM for storing exactly the same data as the data for the EEPROM so that the CPU can always read and write, and transfer of data in the static RAM and data for the EEPROM Controlling EEP
This is a configuration including a ROM control unit.

[0005]

The present invention will be described below with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of the present invention. 1 is a CPU, 2 is an EEPROM controller, 3 is an EEP
ROM 4 is a static RAM. The static RAM 4 is directly connected to the address bus and data bus of the CPU 1. The address bus and data bus of the EEPROM 3 are connected to each bus of the CPU 1 via the EEPROM control unit 2.

Next, the write operation from the CPU 1 to the EEPROM 3 will be described. The EEPROM control unit 2 has a memory that temporarily stacks write data and addresses generated from the CPU 1, and sequentially writes the first written data to designated addresses according to the write specifications of the EEPROM 3. At the same time, the same data is written in the static RAM 4 which is directly connected to the CPU 1 via the bus.

Next, the operation of reading the data on the EEPROM 3 from the CPU 1 will be described. When the data in the EEPROM 3 is normally read from the CPU 1, the data in the static RAM 4 directly connected to the CPU 1 via the bus is read. That is, the data in the EEPROM 3 is indirectly read.

If it is desired to read the actual data in the EEPROM 3, the CPU 1 generates an address for directly reading the data in the EEPROM 3. Receiving this, the EEPROM control section 2 decodes the designated address of the EEPROM 3 and stores the obtained data of the EEPROM 3 in C
Output to the data bus to which PU1 is connected. FIG. 2 shows an example of the memory map viewed from the CPU 1.

Next, the initial setting of the static RAM 4 will be described. When the circuit of the present invention is activated, the data in the static RAM 4 is indefinite. Therefore, EEPR
It is necessary to copy the data of OM3. In that case CPU
As described above, the reference numeral 1 indicates the EE via the EEPROM control unit 2.
The actual data of PROM3 is read, and the data is written in static RAM4, and static RAM4
Initialize the data of.

At this time, the EEPROM control section 2 causes the EEPROM to
No data is written to OM3. That is, EEPR
The OM control unit 2 has a function of not writing to the EEPROM 3. This setting is set by the CPU 1.

[0012]

As described above, the present invention is based on the EEPR.
By replacing the memory space of the OM with the static RAM, the CPU can operate the EEPR without being aware of the physical restrictions on the data writing operation of the EEPROM.
Since data can be written to OM, C
This has the effect of improving the overall processing speed of the PU.

[Brief description of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention.

FIG. 2 is a diagram showing an example of a memory map viewed from a CPU in FIG.

[Explanation of symbols]

 1 CPU 2 EEPROM control section 3 EEPROM 4 static RAM

Claims (1)

[Claims] 1. An EEPROM for storing data
And a CPU to access the data on this EEPROM
A static RAM that stores exactly the same data as the EEPROM and can be read and written by the CPU at all times; and the static RAM data and the EE
EEPROM for controlling exchange with PROM data
A data access method for an EEPROM, comprising: a control unit.