JP3074984B2 - Memory management device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory management apparatus having a program memory page management mechanism for storing a control instruction (POL instruction) for an industrial plant controller or the like.

[0002]

2. Description of the Related Art FIG. 8 is a diagram showing a conventional page management system, in which 1 is a processor for executing a module, 4 is a memory IC for storing an execution module, 3 is a page division of an execution module, A page management table 5 for managing whether pages are allocated to pages is a page bank table for managing a physical address (page base address) of a page corresponding to a page number (page No.) for each page.

The information of the program area of the execution module executed by the processor 1 is stored in basic software (normal operating system;
When each area is divided into pages, the used page number of the area is managed by the page management table 3 for each execution module. For example, the execution module No. 0 is divided into three pages, and the page numbers at that time are 0, 1
If the number is 0 or 3, the OS sends the module number. 0 at the start of execution of page No. 0 from the page management table 3.
0 is loaded into the program counter of the processor 1 and the entry 0 of the page number and the page number. Set the offset from 0.

When executing a module, the processor 1 extracts a page number from the program counter based on a value set in the program counter by the OS, and obtains a physical address of a page corresponding to the page number specified from the page bank table 5. Then take out 100H. The page bank table 5 is a table for managing a physical address (page base address) of a page corresponding to a page number for each page, and is normally stored in a memory.
Next, the physical address of the execution module existing in the memory IC 4 is generated by taking out the offset from the program counter and linking or adding the physical address of the page. Here, the page size can be set by changing the page address (physical address) stored in the page bank table 5.

[0005]

The conventional memory management device is configured as described above. When the processor 1 reads an execution module from the program memory 4, the execution module is stored in the page bank table 5 from the page number of the program counter. Since it is necessary to read the page address and concatenate it with the offset, the following adverse effects occur.
That is, when the page size is set to be small, the number of entries for managing the page address in the page bank table increases, which inevitably increases the used memory and increases the cost. Further, at the time of module execution, high-speed generation of addresses in a memory is required, but the process of memory addressing in the conventional page management is complicated, and the overhead of table access at the time of address generation by a processor is large. Further, when it is desired to know the module No. actually executed by the processor and the page No. being used, there is also a problem that it takes a long time for the determination process.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned problems. The present invention eliminates the need for a page bank table, eliminates the overhead of table access when an address is generated by a processor, and has a simple H / W configuration. It is an object of the present invention to realize a memory management device capable of performing page management by using the same.

[0007]

According to a first aspect of the present invention, there is provided a memory management apparatus which stores a page number assigned to each module, and executes the page management table in response to an instruction execution request from a processor. You
Page number setting means for extracting the page number corresponding to the instruction of the module to be stored and storing the page number, a program counter which operates each time the instruction is executed, and the page number stored in the page number setting means and the program counter. An address generation circuit is provided for accessing the memory from the output and generating an address from which an instruction of the execution module is to be read.

According to a second aspect of the present invention, during execution of a module, it is determined whether or not an address to a memory has exceeded one page from an output of a program counter. The next page number assigned to the module is extracted, and the page number stored in the page number setting means is updated to the newly extracted page number.

A memory management device according to a third aspect of the present invention includes a memory type setting means for setting a memory capacity and a data bus width, and changes the number of carry bits of a program counter according to the set memory type. It was made.

According to a fourth aspect of the present invention, there is provided a memory management apparatus, wherein a flag which is enabled during execution of each module is provided in the page management table, and the module being executed and the module being used in the processor are determined based on the state of the flag. Page number of the
When there is a request to rewrite the module, an unused page
Find the number and in the memory corresponding to that page number,
Write the modified module program and execute it
Stop the module temporarily and replace it with the above module
The module is restarted by the module program . According to a fifth aspect of the present invention, there is provided a memory management device, wherein each of the processors of a multiprocessor having a plurality of processors includes the same page management table and memory, and when one processor goes down, By sending the flag status information of the page management table to other normal processors, bumpless switching between processors is enabled.

[0011]

According to the present invention, when a processor issues an instruction to execute a module, the processor accesses the page management table and extracts the page number assigned to the module. The extracted page number is stored in the page number setting means, and an address generation circuit generates an address of a memory from which the instruction of the execution module is to be sequentially read from the data and the output of the program counter.

When the generated address exceeds one page,
Access the page management table again to extract the remaining page numbers. The data stored in the page number setting means is updated to this new page number, and the address generation is continued.

If memory type setting means is provided and the number of carry bits of the program counter is changed by this data, the present invention can be applied to memories having different memory capacities and data bus widths.

By providing a predetermined flag in the page management table, it is possible to immediately determine the module being executed or the page number being used. For example, the module can be rewritten online or a hot standby operation can be performed by a multiprocessor. Can be easily and quickly achieved.

[0015]

【Example】

Embodiment 1 FIG. Hereinafter, a first embodiment of the present invention will be described with reference to the drawings. In FIG. 1, reference numeral 1 denotes a processor that manages a series of instruction execution operations and generates instruction execution timing, 2 denotes an instruction execution H / W that executes an instruction in response to an instruction execution request from the processor 1, and 3 denotes each execution. Page No. for each module
Is a memory management IC for storing modules, and its space is subdivided in page units. Further, 21 is a status register 21A,
And a register file including a register such as a page number register 21B as a page number setting means; 23, an instruction execution unit that accesses the memory IC 4 to start, decode, and execute an instruction by starting from the main processor; A reference numeral 24 denotes an address generation circuit for generating an address for accessing the memory IC 4 and reading an instruction.

Next, the operation will be described. The execution of the POL instruction is performed by the processor 1 reading out the status register 21A inside the instruction execution H / W2. The instruction execution H / W2 executes one POL instruction when there is a read operation to the register 21A. P
Error information such as a bus error and an operation error during execution of the OL instruction is stored in the status register 21A as a POL instruction execution result status. As a result of the read operation, the processor 1 executes the POL instruction and returns the contents of the status register 21A from the instruction execution H / W2 to the processor 1. Processor 1
Checks the contents of the status register 21A returned from the instruction execution H / W2,
Check whether the OL instruction has been executed normally. Based on the check result, the processor 1 performs an error process corresponding to the error if there is any error, and executes the next POL instruction by accessing the status register 21A again if there is no error.

Here, an address conversion method using the page management table 3 will be described with reference to the flowchart of FIG . When starting the execution module, the processor 1 extracts the page number from the module number from the page management table 3 in S11, and sets the value in the page number register 21B in S12. Here page No.
Indicates an entry of each page.

In the instruction execution H / W2, by linking the page number register 21B set in S21 and the program counter 22 in S22, the POL instruction execution by the reading operation from the processor 1 to the status register 21A in S13. At the timing of
4 is generated.

The program counter 22 indicates the relative address of each page from the base position. As shown in S23, each time the POL instruction is executed, the value is incremented by one.
By this increment operation, it is checked in S24 whether or not an access beyond the page has occurred, and if it has been exceeded, the information is set in the status register 21A in S25.

Normally, the processor 1 repeats the steps from S13 to S14, and the instruction execution H / W2 is S22, S2
3. The control command is executed by repeating the steps of S24.

When one instruction of POL is executed and the address exceeds one page (YES in S24), the information is stored in the status register 21A (S25). S
At 13 the processor 1 sets its status register 21A
When it is determined that an access beyond one page has occurred based on the value of (1), the process returns to S11, and refers to the page management table 3 to check the next page No. corresponding to the module being executed in S12.
Is extracted, the value is set in the page number register 21B inside the instruction execution H / W2, and the instruction execution is restarted in S13.

As described above, in this embodiment, the page management table 3 is effectively used, and the corresponding page N
o is extracted and stored in the page number setting register 21B,
Since the address generation circuit 24 generates an address for directly accessing the memory IC 4 with the output from the program counter 22, the access to the memory IC is managed by using the page bank table and combining the offset with the page address read from this. Compared with the conventional method, the processing content is simplified and the processing speed is improved.

Embodiment 2 FIG. Hereinafter, a second embodiment of the present invention will be described with reference to FIGS. In FIG. 3, 21C
Is a memory type setting register for setting the capacity of the memory IC 4 and the data bus width. The same parts as those in FIG. 1 are denoted by the same reference numerals, and description thereof is omitted.

Next, the operation will be described. The number of necessary addresses of the normally used memory IC 4 differs depending on its capacity and data bus width. For example, 256 kbit SR
The address is 1 even if the data bus width is 1 bit even in the AM element.
Eight are required, and if the data bus width is 4 bits, 16 addresses are required. If the memory capacity changes, the number of addresses also changes. Therefore, it is necessary to change the required number of bits of the program counter 22 used for address generation according to the type of the memory IC 4.

In FIG. 4, the capacity and data bus width of the memory IC 4 are set in advance in the memory type setting register 21C.
, So that the bit position at which the carry of the program counter 22 carries can be decoded from the set value and made variable. For example, a program counter 22 needs 12 bits to count a 4k step instruction per page, but if a 1 k step instruction per page is stored using a small-capacity memory, a 10 bit program counter Therefore, the memory type is set in the memory type setting register 21C, the information is decoded, and the bits 11 and 10 of the program counter 22 are turned off.
Change to F. Thus, the memory type setting register 21C
By changing the bit position for checking the carry of the page of the program counter 22 according to the information described above and connecting it to the page number setting register 21B, it is possible to change the generated address according to the memory type.
Thereafter, the execution of the instruction is performed in the same manner as in the first embodiment.

As described above, the present invention can be applied to devices having different memory capacities and data bus widths as they are, and a wider range of functions and processes can be applied to apparatuses.

Embodiment 3 FIG. Hereinafter, a third embodiment of the present invention will be described with reference to FIGS. In order to perform the maintenance of the program during the process control, it is necessary to minimize the execution interruption time of the module controlling the target process.

Module valid flags 3A, 3B, 3C and 3D are added to the page management table 3 as shown in FIG. 5 to indicate whether the execution module is valid or invalid. The valid flags 3A, 3A of the module currently being executed
B and 3C are each ON.

Here, the module No. being executed. 4,
When there is a program rewrite request from the maintenance tool, in step S31, the processor 1 reads the module number from the page management table 3. 4 (2 pages in FIG. 5) and unused unused pages (FIG. 5).
In the case of No., 40 and No. 46) and retrieve the program sent from the maintenance tool into these page Nos. 40 and No. At the same time, the above combination is added to the page management table 3 (S33). During the program writing operation of the processor 1, the module No. 4 is not interrupted.

When the program write operation is completed, the module No. 4 is temporarily stopped (S3
4), in order to change the module valid flag, the page No. executed so far in S35. 9 and no. Turn off module valid flag 3A in page management table 12
Then, the newly written page No. 40 and No. The module valid flag 3D of 46 is turned ON. When the change of the module valid flags 3A and 3D is completed, the module No. 4 is restarted (S36). Thereafter, the execution of the instruction is the same as in the first embodiment, and a description thereof will be omitted.

As described above, in this embodiment, the module can be rewritten online with simple processing, and the execution stop time required for the rewriting can be extremely short.

Embodiment 4 FIG. FIG. 7 shows a fourth embodiment of the present invention, which is applied to a multiprocessor system using a plurality of controllers. And here, by utilizing the previous flag information, aims at realizing a bar Npuresu switching to normal processor when a processor goes down.

In this multiprocessor system, each of the processors 10 to 1N has all the execution modules of the other processors, and has the same page management tables 31 to 3N and the same program memories 41 to 4N. However, the module validity flags of the page management tables 31 to 3N are valid only for the module being executed by the own processor. For example, in the processor 10, the module No. 9 is valid (31B is ON) and module No. 4, Module No. 63 is invalid (31
A, 31C are OFF). 4 is valid (32A is ON), and module No.
9, Module No. 63 is invalid (32B, 32C is O
FF), a separate module is running on each processor.

Now, when a failure occurs in the processor 10 and an irrecoverable failure is recognized, the processor 10 sends the information 31A, 31 of the module valid flag of the page management table 31 to another processor, for example, the processor 11.
The processor 11 can know the module that has been executed by the processor 10 and the page number that has been used up to now only by notifying the B and 31C. Therefore, the module valid flag of the page management table 32 in its own processor is provided. By changing ON / OFF of 32A, 32B, and 32C, the proxy processing operation of the processor 10 can be started immediately.

Embodiment 5 FIG. In each of the above-described embodiments, means for determining whether the address output from the address generation circuit 24 has exceeded one page is provided. If the address has exceeded, the remaining page number is extracted from the page management table 3, and Although the configuration is such that the input is made to the setting register 21B, if the number of pages allocated to each module is all one, it is natural that such a determination means becomes unnecessary.

[0036]

As described above, the memory management device according to the present invention includes the predetermined page management table, the page number setting means, the program counter, and the address generation circuit. Can be processed at a high speed with a relatively inexpensive and simple configuration.

Further, if it is determined whether or not the generated address exceeds one page and the remaining page number is extracted and set from the page management table when the generated address is exceeded, the required memory capacity differs greatly depending on the module. It is easy to apply to

Furthermore, if the number of carry bits of the program counter is changed according to the type of memory, complicated circuit design according to each type of memory can be avoided, and the cost and period required for development and design can be greatly reduced. Is realized.

By providing a predetermined flag in the page management table, the module being executed or the page number being used can be immediately identified , and the
Even during execution, the execution module can be rewritten,
Maintenance is Ru can easily quickly. Further, by providing the flag in each page management table of the multiprocessor, it is possible to switch bumpless to a normal processor when a certain processor goes down.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a memory management device according to a first embodiment of the present invention.

FIG. 2 is a flowchart illustrating a processing operation of the memory management device of FIG. 1;

FIG. 3 is a block diagram showing a memory management device according to a second embodiment of the present invention.

FIG. 4 is a block diagram showing a carry change method of a program counter 22 in FIG. 3;

FIG. 5 is a block diagram showing a memory management device according to a third embodiment of the present invention.

FIG. 6 is a flowchart showing a processing operation of the memory management device of FIG. 5;

FIG. 7 is a block diagram showing a memory management device according to a fourth embodiment of the present invention.

FIG. 8 is a block diagram showing a conventional memory management device.

[Explanation of symbols]

 Reference Signs List 1 processor 2 instruction execution H / W 21 register file 21A status register 21B page number setting register 21C memory type setting register 22 program counter 23 instruction execution unit 24 address generation circuit 3 page management table 4 memory IC

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁷ , DB name) G06F 12/00-12/06

Claims (5)

(57) [Claims] An instruction execution request from a processor is received.
A memory management device that includes a memory that divides a module executed by the H / W into pages and stores the module, and reads out an instruction of a module to be executed in response to an instruction execution request of the processor from the memory; A page management table for storing page numbers assigned to the modules, and a module to be executed from the page management table in response to an instruction execution request from the processor.
Page number setting means for extracting the page number corresponding to the instruction of the file and storing the page number, a program counter which operates each time the instruction is executed, and the page number stored in the page number setting means and the output of the program counter And an address generation circuit for generating an address from which the memory is accessed to read the instruction of the execution module. 2. During execution of a module, it is determined from the output of the program counter whether or not the address to the memory has exceeded one page, and if it has, the next page number assigned to the module is extracted from the page management table. And
2. The memory management device according to claim 1, wherein the page number stored in the page number setting means is updated to the newly extracted page number. 3. The memory device according to claim 1, further comprising a memory type setting means for setting a memory capacity and a data bus width, wherein the number of carry bits of the program counter is changed according to the set memory type. 3. The memory management device according to 2. 4. A flag which becomes effective during execution of each module is provided in the page management table, and a module being executed and a page number being used in the processor are determined from the state of this flag, and
If there is a request to rewrite the module during execution,
Search for the page number for the
Write the modified module program in the memory,
Stop the above running module and modify it instead
Module restart by the above module program
4. The memory management device according to claim 1, wherein the memory management device performs an operation . 5. A multiprocessor having a plurality of processors, wherein each of the processors has the same page management table and memory, and the page management table has
Provide a flag that will be enabled during the execution of the module,
Running on this processor from the state of this flag
Module and page number in use can be determined
Claims and, if one processor is down by sending the information of the state of the flag in the page management table of the processor to other normal processors, characterized in that the enabling bumpless switching between processors
4. The memory management device according to any one of 1 to 3 .