JP2853593B2 - Download device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a download device for downloading firmware referenced by a CPU (Central Processing Unit) from a host device, and more particularly to a download device for temporarily downloading firmware to a work area.

[0002]

2. Description of the Related Art The functions of a system having a CPU are mainly determined by firmware that enumerates operations to be performed by the CPU. Therefore, when the function of the system is provided with expandability, the firmware is generally downloaded from a higher-level device to a rewritable storage medium instead of being stored in a ROM (read only memory). By changing the firmware to be downloaded, the functions of the system can be variously changed. When executing the downloaded firmware, the referenced firmware itself is
It may be rewritten by the PU. For example, firmware stored in the memory may be destroyed by the CPU due to a bug (logical error in the program). For this reason, the firmware is stored in an area referred to during operation of the CPU, and is also stored in a nonvolatile memory such as a flash EEPROM (electrically erasable programmable read only memory) for storage. ing.

FIG. 6 shows an outline of a configuration of a system for transferring downloaded firmware to a flash EEPROM and storing it. The CPU 101
It is a circuit device that performs the central function of the system, and performs various processes according to the downloaded firmware. Various circuit devices are connected to the CPU 101 through various buses 102 such as an address bus and a data bus. The ROM 103 is a memory for storing a system startup program and various fixed data. The work memory 104 is an area for downloading firmware and a random access memory for temporarily storing data required when the CPU 101 executes processing according to the firmware. The higher-level interface unit 105 is a circuit device that interfaces with a higher-level device (not shown) that is a supply source of firmware to be downloaded. The flash EEPROM 106 is a rewritable memory capable of holding stored data even when the power is turned off, and stores downloaded firmware for storage.

FIG. 7 shows a circuit configuration around a working memory and a flash EEPROM in FIG. The working memory 104 has an address signal 111 having a width of 22 bits and a data signal 112 having a width of 8 bits.
Write control signal 113 instructing data writing
And a read control signal 114 instructing data reading. Working memory 104 and flash EE
The PROMs 106 are connected by the bus 102. A write control signal 115 for instructing writing and an address signal 116 are input to the flash EEPROM 106. These are signals output from the CPU shown in FIG.

FIG. 8 shows an arrangement of an address space in the system shown in FIG. An area within a predetermined range from address 0 is allocated as an address space 121 for ROM. When the power is turned on or when a reset switch (not shown) is pressed, the program is executed from address 0, so that the start-up program stored in the ROM is executed. ROM area 1
A work area 122 subsequent to 21 is an area for temporarily storing data necessary for executing the firmware.
The work area 122 temporarily stores firmware downloaded from a higher-level device. The firmware area 123 is an area for storing firmware referred to by the CPU 101 during execution.

[0006] The firmware downloaded from the host device is temporarily stored in the work area 122. And
The downloaded firmware is checked for errors using a parity code. After confirming that there is no error, the firmware stored in the work area 122 is updated by the CPU 101 to the flash EEPROM 10.
6 is transferred. By temporarily storing the data in the work area 122 without directly downloading it to the flash EEPROM 106, it is possible to prevent the storage content of the flash EEPROM 106 from being rewritten with erroneous firmware.

After being stored in the flash EEPROM 106, the firmware in the work area 122 is transferred to the firmware area 123. Then, at the time of execution, the farm area 1
23 firmware is referred to by the CPU 101, and the work area 122 is used as a work area at the time of execution. Thus, at the time of execution, the arrangement of the firmware is fixed in the firmware area 123 and the arrangement of the work area is fixed in the work area 122, so that variables and the like can be allocated to fixed addresses , thereby facilitating the design of the firmware. You can do it.

Japanese Patent Application Laid-Open No. 3-99327 discloses a download device in which firmware is downloaded to a work area, and the addresses of the work area and the firmware area are exchanged when the firmware is executed. In this apparatus, when downloading the firmware, a predetermined storage unit is initialized to a state where it is arranged in the work area.

[0009]

When the firmware is downloaded to the work area and transferred to the firmware area, it takes time to transfer the data from the work area to the firmware area in addition to the time for downloading. There is a problem that updating takes a long time. As disclosed in Japanese Patent Laid-Open No. 3-99327, if the address arrangement of the work area and the firmware area is changed after the firmware is downloaded to the work area, the time for actually transferring the firmware becomes unnecessary. Therefore, the time required for updating can be reduced. However, the downloaded firmware is flash EE
When the data is stored in a backup memory such as a PROM, a copying operation from the work area to the backup memory is also required. Conventionally, flash EEPROM from work area
Since the transfer to the OM is performed by the CPU, the CPU cannot perform other processing until the transfer is completed, and the time for stopping the system with the update of the firmware becomes longer. is there.

In the downloading apparatus disclosed in Japanese Patent Laid-Open Publication No. 3-99327, the arrangement of the storage means is initialized at the time of downloading, so that when downloading new firmware, the previous firmware is destroyed. Would. For this reason, after the download is started, the process cannot proceed according to the previously downloaded firmware, and there is a problem that the time during which the system is stopped becomes longer.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a download apparatus which can reduce the time for stopping the system when updating firmware.

[0012]

Means for Solving the Problems] In the present invention of claim 1, wherein a first area allocated as an area for storing data to be rewritten during execution on the address space of (i) a central processing unit, (b) A second area allocated as an area for storing data that is only referenced during execution on the address space of the central processing unit; and (c) a predetermined area in which only the reference transferred from the higher-level device to the first area is performed. a data storage means for storing the data, (d) and non-volatile backup memory is provided for storing predetermined data described above stored by the data storage means for the storage, the first of these (e) And the second area and
A data bus for connecting the backup memory, and ( f ) connecting between the first and second areas and the backup memory.
A local bus independent of the data bus,
(G) operable in parallel with the central processing unit connected to the data bus, and transferring the predetermined data stored by the data storage means from the first area to the backup memory via the local bus. Transfer means for copying; and (h) address arrangement exchange means for exchanging the arrangement of the first area and the second area in the address space after the predetermined data is copied to the backup memory. Let me.

[0013]

[0014]

[0015]

[0016]

[0017] That is, in a first aspect of the present invention, the data stored in the first region, is copied to the backup memory by the operable transfer means in parallel with the central processing unit. This allows the central processing unit to proceed with the processing based on the data stored in the second area during the execution of the copying operation to the backup memory. The claim
In the invention described in (1), the first and second regions and the backup
Local between memory and memory independent of data bus
A bus is provided, and the transfer means is controlled by the data storage means.
Is stored in the first area.
Copy to this backup memory via local bus
I am trying to.

According to the second aspect of the present invention, (a) a first area allocated as an area for storing data to be rewritten during execution on the address space of the central processing unit;
A second area allocated as an area for storing data which is only referred to during execution on the address space of the central processing unit, and (c) only a reference transferred from a higher-level device to the first area is performed; A data storage means for storing predetermined data to which an error detection code is added, and a non-volatile backup memory prepared for storing the predetermined data stored by the data storage means for storage; (D) In these first and second areas
A data bus for connecting the backup memory
(E) Between the first and second areas and the backup memory
And a local bus independent of the data bus,
(F) error checking means for checking whether there is an error in the data stored in the first area based on the error detection code;
(G) operable in parallel with the central processing unit connected to the data bus, and when no error is detected by the error checking means, stores the predetermined data stored in the first area in the backup memory. Transfer means for copying via a local bus; and (h) an address for replacing the arrangement of the first area and the second area in the address space after the predetermined data is copied to the backup memory. The arrangement replacement means is provided in the download device.

That is, in the second aspect of the present invention, after confirming that there is no error in the data stored in the first area, the contents of the backup memory are updated. In the invention described in claim 2, the first and the second
Between the data area and the backup memory
Has an independent local bus, and the transfer means
The predetermined data stored by the data storage means;
Data from the first area to this backup memory
Copying is done via the bus.

According to the third aspect of the present invention, the address arrangement exchanging means exchanges the arrangement in the address space by converting a predetermined bit logical value of the address signal output from the central processing unit. I have.

That is, in the third aspect of the present invention, the arrangement in the address space is exchanged by converting the logical value of a predetermined bit in the address signal output from the central processing unit. Thus, the address arrangement can be switched with a simple circuit configuration.

[0022]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The present invention will be described in detail below with reference to embodiments.

FIG. 1 shows the overall configuration of a download apparatus according to an embodiment of the present invention. The same parts as those in FIG. 3 are denoted by the same reference numerals, and description thereof will be omitted as appropriate. The bank memory circuit 11 is connected to the bus 102. The entire storage area of the bank memory circuit 11 is divided into two areas, bank 1 and bank 2, and these address arrangements can be interchanged. The bank switching circuit 12 exchanges the addresses of the banks 1 and 2 in accordance with a predetermined bank select signal output from the output port of the CPU 101. The transfer control circuit 13 stores the firmware downloaded from the host device in the flash EEPROM.
This is a circuit device for transferring data to the OM 106. The transfer control circuit 13 and the address signal lines of the flash EEPROM 106 and the bank memory circuit 11 are connected to the local bus 14.
Connected by By transferring the data through the local bus 14, the transfer control circuit 13
The firmware can be transferred in parallel with the operation.

FIG. 2 shows a circuit configuration of a main part of the download apparatus shown in FIG. The address signal 21 output from the CPU is input to the bank memory circuit 11. The bank memory circuit 11 has a CPU
, A write control signal 22, a read control signal 23, and a data signal 24. The CPU outputs an address signal 21 having a 22-bit width, and the bank switching circuit 12 receives an address signal 25 for two bits from the upper side. Further, a bank select signal 26 is input to the bank switching circuit 12 from an output port of the CPU. The memory bank circuit 12 has a memory area of 2 megabytes, and is divided into two banks of 1 megabyte.

When the bank select signal 26 is "0",
The address signal 21 output from the CPU is directly input to the memory bank circuit 11. Bank select signal 2
When 6 is "1" and the most significant bit of the address signal output from the CPU is "1", the address signal of the second bit from the upper bit is inverted and the memory bank circuit 1
1 is input. Thus, when the bank select signal 26 is "1" and "0", the address arrangement of the banks 1 and 2 is switched. The address signal 27 of the second bit from the upper side output from the bank switching circuit 12 can be obtained by taking the exclusive OR of the upper two bits of the address signal output from the CPU.

The transfer control circuit 13 has a flash EEP
Transfer start signal 28 instructing start of transfer to ROM 106
And a clock signal 29 for determining the transfer rate. The transfer control circuit 13 outputs an address signal used for transferring the firmware.
M106 and the bank memory circuit 11. Further, the memory bank circuit 11 and the flash EEPROM 1
06 is also connected by the local bus 14 for its data signal. The timing of reading data from the bank memory circuit 11 and the flash EEPROM 10
6, a timing signal 31 defining the timing of writing data to the bank memory circuit 1
1 is input to the flash EEPROM 106.
Transfer control circuit 13 flashes firmware to EEP
During the transfer to the ROM 106, the address for accessing the bank 1 is supplied from the local bus 14. The address for the bank 2 is supplied from the CPU. This allows the CPU to execute other processing in parallel with the transfer of the firmware by the transfer control circuit 13.

FIG. 3 shows the arrangement of the address space in the download apparatus shown in FIG. RO
M area 41 is from address 0 to 1FFFFFH (hexadecimal notation)
Up to 2 megabytes of space have been allocated. 20
Address space 42 from 0000H to 3FFFFFFH
Is assigned a memory bank circuit. The diagram on the left shows the arrangement of the address space when the bank select signal is "0". At this time, bank 1 is arranged from 200,000H, and bank 2 is arranged at 300,000H.
H. The diagram on the right shows the address space arrangement when the bank select signal is "1". At this time, the bank 2 is arranged from 200000H, and the bank 1 is arranged from 300000H, and the address arrangement is reversed according to the bank select signal. The address space 43 of 300000H to 3FFFFFH is allocated to an area where firmware is arranged at the time of execution. In addition, 200000H-2FF
The FFFH address space 44 is allocated so as to be used as a work area at the time of execution.

FIG. 4 shows the flow of processing performed when downloading firmware. CP
U101 stores the firmware downloaded from the higher-level device in the bank currently arranged in the work area 44 (step S101). At this time, it is assumed that the bank 1 is arranged in the work area 44. When all the data has been stored, the CPU 101 checks whether or not there is an error in the downloaded firmware by a parity check (step S102).
If there is an error (step S103; Y), an error message is sent to the host device that is the firmware supply source, notifying that the transferred data has an error (step S104). If there is no error (step S103; N), the transfer control circuit 13 is activated (step S105), and the firmware stored in the bank 1 is copied to the flash EEPROM 106. Since the transfer is performed via the local bus 14 shown in FIG. 3, the CPU 2 can freely access the bank 2. Here, the CPU 101 executes another process using the firmware existing in the bank 2 (step S106). When the transfer by the transfer control circuit is completed (step S107; Y), the CPU 10
1 outputs "1" as a bank select signal, and swaps the address arrangement of bank 1 and bank 2 (step S1).
108). Then, the CPU proceeds with the process based on the updated firmware stored in bank 1 (step S109). At this time, the bank 2 is used as a work area.

FIG. 5 shows waveforms at various parts of the circuit shown in FIG. 2 when the firmware is downloaded. In synchronization with the data downloaded from the host device, the CPU 101 sends an address signal 21 for storing the firmware to the memory bank circuit 11 (a in the figure).
Is output. The address signal 21 changes from 200,000H to 1
The data is sequentially output in increments. In the figure, the state of this increase is simply indicated by numerals 1 to 4. Address signal 2
1, a write control signal 22 (b in the figure) from the CPU 101 is supplied to the bank memory circuit 11. Bank 1
Firmware is stored all and the time T ₁₁ after the parity check is completed, CPU 101 outputs the transfer start signal 28 (Fig. C) to the transfer control circuit 13.

After receiving the transfer start signal 28, the transfer control circuit 13 outputs a clock signal 29 for defining the transfer rate.
A timing signal 31 (FIG. 3E) and an address signal (FIG. 5F) are output in synchronization with (FIG. 4D). This address signal is supplied to the memory bank circuit 11 through the local bus 14.
Is supplied to the flash EEPROM 106. The value of the address signal is 200000 corresponding to the top of bank 1.
It increases by one from H. The state of the increase is indicated by numerals 1 to 4 corresponding to FIG. While the transfer control circuit 13 is performing the transfer of the firmware, the CPU 101 accesses the bank 2 to execute other processing, and the address signal 21 is output after the transfer start signal 28 is output. .

As described above, the firmware stored in the bank 1 is transferred to the flash EEP by the transfer control circuit 13.
Since the bank 2 can be accessed during the transfer to the ROM 106, the CPU 101 can execute an arbitrary process using the bank 2. Further, by switching the address arrangement between the bank 1 and the bank 2, 3000 data can be transferred without transferring from the bank 1 to the bank 2.
Firmware can be located after 0H.

In the above-described embodiment, the firmware is stored in the bank 1 when the firmware is downloaded. However, if the bank 2 is arranged in the work area at that time, the firmware is stored in the bank 2. No. Also,
Flash EEPROM as backup memory
However, any rewritable storage medium that can retain the stored contents even when the power is turned off may be used. For example, a disk device may be used. Further, it is not necessary to allocate the entire ROM area to the ROM.
If a part of this is allocated as a working memory space, a sufficient working area can be ensured even during transfer to the flash EEPROM. Further, the ROM area does not need to be fixedly provided in the address space of the CPU, and may be accessed by the CPU only at the time of startup after power is turned on.

[0033]

As described above, according to the first aspect of the present invention, the transfer means for copying data to the backup memory can operate in parallel with the central processing unit. The device can proceed with processing based on the data stored in the second area. For example, when downloading firmware as data to be referred to only, other processing can be executed even during transfer to the backup memory, so that the system downtime associated with updating the firmware can be further reduced. I
In the present invention, the first and second areas and the backup
Local bus independent of the data bus connecting the memory
And the transfer means is stored by the data storage means.
Predetermined data is transferred from the first area to the backup memory.
Copy via a local bus to
Transfer processing to backup memory by hardware-like processing
Can minimize the effect of processing on other processes.
You.

[0034]

[0035]

According to the second aspect of the present invention, after confirming that there is no error in the downloaded data,
The contents of the backup memory are updated. Thus, it is possible to prevent the contents of the backup memory from being rewritten by data having an error. Moreover, in the present invention, the first and second regions are
Connection between backup memories and independent of data bus
A local bus is provided, and transfer means is provided by data storage means.
The specified data stored in the first area is
Copy to the up memory via the local bus
Backup memo by hardware processing
Minimizes the effect of transfer to the directory on other processes
be able to.

According to the third aspect of the present invention, the arrangement in the address space is exchanged by converting the logical value of a predetermined bit in the address signal output from the central processing unit. The address arrangement can be exchanged with a simple circuit configuration.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of an entire download apparatus according to an embodiment of the present invention.

FIG. 2 is a block diagram showing a circuit configuration of a main part of the download device shown in FIG.

FIG. 3 is an explanatory diagram showing an address space arrangement in the download device shown in FIG. 1;

FIG. 4 is a flowchart showing a flow of processing performed when downloading firmware.

FIG. 5 is a diagram showing various waveforms representing signal waveforms of respective units when firmware is downloaded.

FIG. 6 is a block diagram showing a configuration of a conventionally used download device.

7 is a block diagram showing a circuit configuration of a main part in the conventional download device shown in FIG.

FIG. 8 is an explanatory diagram showing an address space arrangement in the conventional download device shown in FIG. 6;

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 11 Bank memory circuit 12 Bank switching circuit 13 Transfer control circuit 14 Local bus 43 Farm area 44 Work area 101 CPU 105 Upper interface unit

────────────────────────────────────────────────── ─── Continuation of the front page (56) References JP-A-7-200306 (JP, A) JP-A-6-95988 (JP, A) JP-A-6-78086 (JP, A) 276328 (JP, A) JP-A-5-274154 (JP, A) JP-A-2-22748 (JP, A) JP-A-3-78848 (JP, A) JP-A-5-197559 (JP, A) (58) Field surveyed (Int.Cl. ⁶ , DB name) G06F 9/06, 9/445, 12/16

Claims (3)

(57) [Claims] 1. A first area allocated as an area for storing data to be rewritten during execution on an address space of a central processing unit, and data to be referred to only during execution on an address space of the central processing unit. A second area allocated as an area to be read, data storage means for storing predetermined reference data transferred only from the higher-level device in the first area, and the predetermined area stored by the data storage means. Non-volatile backup memory prepared for storing the data of the first and second areas and the backup memo
Between the first and second areas and the backup memory.
A local bus connected to and independent of the data bus, and operable in parallel with a central processing unit connected to the data bus , wherein the predetermined data stored by the data storage means is stored in the first data bus . Transfer means for copying from the area to the backup memory via the local bus, and after the predetermined data is copied to the backup memory, the arrangement of the first area and the second area in the address space is exchanged. A download device comprising: an address arrangement replacing unit. 2. A first area allocated as an area for storing data to be rewritten during execution on the address space of the central processing unit, and data which is only referred to during execution on the address space of the central processing unit. A second area allocated as an area to be read, and data storage means for storing predetermined data to which only a reference transferred from a higher-level device and to which an error detection code is added is stored in the first area. A non-volatile backup memory prepared for storing the predetermined data stored by the data storage means for storage, a first and a second area, and a backup memo;
A data bus for connecting the re, between said first and second regions and the backup memory
A local bus connected to and independent of the data bus, error checking means for checking whether there is an error in the data stored in the first area based on the error detection code , and a local bus connected to the data bus. said central processing unit in parallel to be operable with, the local bus said predetermined data stored in said first region when no error is detected by the error check means in said backup memory and
Transfer means for copying the predetermined data in the backup memory, and an address arrangement exchanging means for exchanging the arrangement of the first area and the second area in the address space after the predetermined data is copied to the backup memory. A download device characterized by the above-mentioned. 3. The central processing unit according to claim 1, wherein
Predetermined bit of address signal output from device
By converting the logical value of
2. The arrangement of claim 1, wherein
The download device according to claim 2 .