JP2581057B2 - Evaluation microcomputer - Google Patents

Description

The present invention relates to an evaluation microcomputer, and more particularly to an evaluation microcomputer.
The present invention relates to an evaluation microcomputer for evaluating a program of a chip microcomputer.

[Related Art] In recent years, one-chip microcomputers in which program instructions are stored in an internal program memory have been adopted in various devices, and program instructions required in devices to which one-chip microcomputers are also applied. In accordance with the number of steps, the basic function is the same, but the storage capacity of the program memory is changed, and the dimensions of the semiconductor substrate for realizing the one-chip microcomputer are appropriately selected.
The manufacturing cost of a one-chip microcomputer is reduced.

Therefore, when evaluating the program instructions contained in the family one-chip microcomputer, all the program instructions in the same family must be evaluated by the evaluation microcomputer mounted on the program development tool. Therefore, the conventional microcomputer for evaluation is designed to have the same program memory capacity as that of the largest program memory capacity in the same family, and the program memory is stored in the program memory of the one-chip microcomputer to be evaluated during the actual evaluation. It was used by limiting it to the same value as the memory capacity.

The following method is known as the capacity limitation of the program memory in such a conventional evaluation microcomputer. First, in the first method, external pins corresponding to the number of types of one-chip microcomputers constituting a family are provided in advance, and an evaluation microcomputer determines data relating to memory capacity based on signals supplied to the external pins. In this method, the available memory capacity is determined.

On the other hand, in the second method, a mode register for storing information for determining the memory capacity is prepared in the evaluation microcomputer in advance, and the mode register is stored in the mode register using an instruction from the evaluation microcomputer. A memory capacity that can be used by storing information for determining the memory capacity has been determined.

[Problems to be Solved by the Invention] However, in the above-described conventional evaluation microcomputer, when the first method is employed to limit the capacity of the program memory, there is a problem that the number of external pins increases. For example, if there are four types of one-chip microcomputers constituting the same family, two external pins are required, and if eight types, three external pins are required. Therefore, when the first method is adopted, the number of external pins increases, which causes a problem that the device becomes large and expensive.

On the other hand, when the above-described second method is adopted, the evaluation is interrupted while the information on the memory capacity is written in the mode register, and a problem occurs that the evaluation target program is not accurately evaluated. That is, to write information about the memory capacity to the mode register, the evaluation of the program is temporarily suspended while the reset signal is input, and the information about the memory capacity is written to the mode register. However, many microcomputers have a specification such that a special mode such as a standby mode is passed at the time of reset. Therefore, if the evaluation of the program is interrupted by writing the mode register, accurate evaluation cannot be performed.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and an object of the present invention is to provide an evaluation microcomputer capable of accurately evaluating a program without increasing the number of external pins.

[Means for Solving the Problems] The gist of the present invention is to provide a program counter for specifying an address of a program memory having a storage capacity exceeding a storage capacity required for storing an addressable instruction code, and the program counter. And an inspection means for reading and inspecting the instruction code specified in the step (a), wherein data relating to a storage capacity for holding the instruction code to be evaluated is set in the program counter when the evaluation microcomputer is initialized. A mode register that stores the data and controls the program counter, and a writing unit that supplies a write signal to the mode register in response to an initial reset signal generated at the time of initialization. It is to have.

[Operation of the Invention] In the evaluation microcomputer according to the above configuration, a predetermined value is set in the program counter only when an initial reset signal is generated, such as when the power is turned on, and information on the memory capacity is read from the corresponding address of the program memory. It is. The information on the memory capacity is written into the mode register based on the initial reset signal, and is used to limit the storage capacity of the program memory.

However, at the time of a normal reset, a predetermined value is not set in the program counter, so that information on the memory capacity is not transferred to the mode register at the time of a normal reset.

[Example] Hereinafter, an example of the present invention will be described with reference to the drawings.

First Embodiment FIG. 1 is a block diagram showing a configuration of a first embodiment of the present invention. In the figure, 1 is an evaluation microcomputer, 2 is a clock signal, 3 is an initial reset signal,
4 is a mode register read clock generation gate, 5
Indicates a mode register. The evaluation microcomputer 1 sends the value of the program counter 6 to the program memory 7 via the address bus 7, and the program memory 7 stores the data held at the address designated by the value of the program counter 6 in the evaluation microcomputer. The data is supplied to a designated unit such as a decoder of the computer 1. However, decoders and the like are not relevant to the understanding of the present invention and are omitted. The above program memory 7
Are assigned in advance for storing information relating to the memory capacity, and the predetermined address is designated by the program counter 6 when the initial reset signal is applied.

Next, the operation of the evaluation microcomputer shown in FIG. 1 will be described. When the power supply of the evaluation microcomputer 1 is turned on, a predetermined value is set in the program counter 6, and the predetermined address of the program memory 8 is designated based on the value. As a result, information on the memory capacity is read from the predetermined address, and the mode register read clock gate 4 supplies the write signal 11 to the mode register 5 while the initial reset signal 3 and the clock signal 2 are both active. The information on the memory capacity read from the program memory 8 is written in the mode register 5. The mode register 5 controls the program counter 6 via the dedicated signal line 10 based on the information on the stored memory capacity, and limits the memory capacity of the program memory 8. Since the initial reset signal is generated only at the time of initialization such as when the power is turned on, the evaluation of the program is not interrupted even if a normal reset signal is generated thereafter.

The first embodiment will be described more specifically as follows. For example, erasable read-only memory (hereinafter referred to as EPROM) 27256 (32K × 8
Bit), the microcomputer used for evaluation is of the buggy back type (type in which the EPROM is mounted directly on the top of the microcomputer). Although the address width is only 14 bits, the most widely used EPROM272
Using 56 or more EPROMs requires a minimum of 15 bits. Therefore, the actually used memory capacity is 4
Kilobytes, 8 kilobytes, 16 kilobytes,
No more than 16 kilobytes of memory space is used. That is,
As shown in FIG. 2, in the case of 4 kilobytes, 8 kilobytes, and 16 kilobytes, only the memory spaces indicated by 21, 222, and 23 are used as the memory of the microcomputer. Therefore, information on the memory capacity can be stored at a predetermined address in the unused memory space 24, for example, at address 7FFF. Such information may be, for example, "00" for 4 kilobytes, "01" for 8 kilobytes, and "02" for 16 kilobytes. In an evaluation microcomputer equipped with such an EPROM, when an initial reset signal is applied, the program counter designates the address “7FFF” and transfers information on the memory capacity to the mode register.

Second Embodiment FIG. 3 is a block diagram showing a configuration of a second embodiment of the present invention. In the second embodiment, a program counter 8 is provided in an evaluation microcomputer. In the second embodiment, since the EPROM is used as the program memory 8, the memory capacity is required to store at least information on the memory capacity in the memory capacity necessary for storing the maximum program of the microcomputer to be evaluated. To the value obtained by adding the required memory capacity.

In order to evaluate a program by the evaluation microcomputer, information on the memory capacity is stored in advance in the address space 30 of the program memory 8 in addition to the program to be evaluated, and then the program is evaluated in the same manner as in the first embodiment. Perform an evaluation.

[Effects of the Invention] As described above, according to the present invention, a predetermined value is set in the program counter based on the initial reset signal, and the address of the program counter corresponding to the value can be used by the program counter. A mode register for storing information about the memory capacity and holding the information about the memory capacity based on the initial reset signal to limit the capacity of the program memory is further provided. There is no need to add to the computer, no increase in external pins, and no interruption in program evaluation. Therefore, it can be adopted for an evaluation computer having a limited memory capacity, and can be reduced in size and cost, and
The effect is obtained that accurate program evaluation can be performed.

[Brief description of the drawings]

FIG. 1 is a block diagram illustrating a configuration of a first embodiment of the present invention, FIG. 2 is a block diagram illustrating a memory space of the first embodiment, and FIG. 3 is a block diagram illustrating a configuration of the second embodiment. is there. 1 ... Evaluation microcomputer, 2 ... Clock signal, 3 ... Initial reset signal, 4 ... Mode register read clock generation gate, 5 ... Mode register, 6 ... Program counter, 7 ... Address bus, 8 …… Program memory 9… Data bus 10… Dedicated signal line for memory capacity determination information 11… Mode register write signal 30… Address space for information related to memory capacity

Claims (1)

(57) [Claims] 1. A program counter for designating an address of a program memory having a storage capacity exceeding a capacity necessary for storing an addressable instruction code, and an inspection for reading and inspecting the instruction code specified by the program counter. In the evaluation microcomputer provided with the means, data on the storage capacity for holding the instruction code to be evaluated is stored at a predetermined address set in the program counter when the evaluation microcomputer is initialized, and An evaluation microcomputer comprising: a mode register for storing the program counter and controlling the program counter; and writing means for supplying a write signal to the mode register in response to an initial reset signal generated at the time of the initialization.