JPH069032B2 - Single chip microcomputer - Google Patents

Description

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a microcomputer incorporating a ROM and a RAM, and particularly to an R during dynamic screening.
The present invention relates to a novel configuration of a single chip microcomputer in which it is effective to operate an AM.

2. Description of the Related Art A general configuration of a conventional single-chip microcomputer is shown in FIG.

As shown in FIG. 2, this single-chip microcomputer has Cs each coupled to an internal data bus 25.
It has a PU 21, a RAM 22, a ROM 23, and an input / output circuit 24. An instruction stored in the ROM 23 is transferred to the CPU 21 via an internal data bus, and the CPU 21 executes a predetermined operation according to the input instruction.

FIG. 3 is a diagram schematically showing the structure of the RAM incorporated in the microcomputer as described above.

The write operation in this RAM is as follows. First, a RAMWR from a CPU (not shown)
The write circuit 33 is activated by a logical product signal of the signal and the RAMEN signal indicating the RAM memory space,
The data on the internal data bus 35 is written in the RAM cell section 31. A cell for writing data is indicated by the RAM address decoder 32.

The read operation in this RAM is as follows. RAMEN signal from CPU and RAMRD
The read circuit 34 is activated by a logical product signal with the signal and output to the data bus 35. Here, the RAM cell 31 storing the data to be read is designated by the RAM address decoder 32.

A static BT screening method and a dynamic BT screening method are generally carried out as a bias temperature: temperature / voltage application screening method (hereinafter referred to as BT screening method) of a single-chip microcomputer as described above.

The static BT screening method supplies only a power supply voltage to a device in a non-operating state and leaves it in a high temperature state. On the other hand, the dynamic BT screening method is a method in which a signal is externally supplied to a device, the device is put into an operating state, a voltage is sometimes applied to an internal signal line, the device is left in a high temperature state, and BT screening is performed.

Generally, in a microcomputer having a built-in ROM, it is possible to perform a BT screening equivalent to a dynamic BT by applying an external clock signal by adding a function of sequentially executing the instructions stored in the built-in ROM in advance. , Is also actually done.

Problems to be Solved by the Invention However, in the conventional single-chip microcomputer as described above, when the method as described above is carried out, the contents of the built-in ROM differ for each customer. The behavior is different. That is, in a single-chip microcomputer loaded with a certain program, the amount of RAM used is small through one-time dynamic BT screening, while in a single-chip microcomputer loaded with another program, during the dynamic BT screening, In most cases, the RAM is active.

Therefore, when a plurality of single-chip microcomputers are simultaneously subjected to BT screening, there is a problem that the reliability of BT screening is different for each single-chip microcomputer.

According to the present invention, there is provided a RAM coupled to an internal bus via a read circuit and a write circuit, and a built-in ROM coupled to the internal bus via a read circuit and storing instructions. A single-chip microcomputer for executing an operation of reading an instruction stored in the built-in ROM according to a ROM read signal, wherein the contents of the bus read from the ROM are read by the read signal in a test mode. There is provided a single-chip microcomputer including a control circuit that controls to execute an operation of writing to a RAM.

EXAMPLES Next, the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of a RAM according to an embodiment of the present invention and corresponds to FIG. 3 described in the prior art.

First, the normal operation will be described. RA in normal operation
When writing data to M cell 1, C not shown
RAMEN and RAMWR signals from PU are "1"
Therefore, the output “1” of the AND circuit 8 that outputs the logical product of these is input to one of the OR circuits 7. Thus, O
The write circuit 3 operates by the output of the R circuit 7, and the data on the internal data bus 5 is transferred to the RAM address decoder 2
The data is written in the RAM cell unit 1 indicated by.

In addition, when reading the data on the RAM cell unit 1, C
RAMEN and RAMRD signals from PU are "1"
Since the output of the AND circuit 6 which is the logical product of these becomes "1", the read circuit 4 becomes active and the RAM cell 1 shown by the RAM address decoder 2
The above data is output to the internal data bus 5.

The operation of such a RAM during dynamic BT is as follows.

First, the TEST signal is set to "1" from the outside. Also, R
The OMRD signal is a read signal for reading the contents of the ROM to the internal data bus so that the instructions stored in the built-in ROM are sequentially executed.

Therefore, when the contents of ROM are read to the data bus, R
The OMRD signal becomes "1" and the output of the AND circuit 9 becomes "1". In this way, since the output of the OR circuit 7 becomes "1", the write circuit 3 becomes active, and the data on the data bus 5 (the instruction read from the ROM)
Writing to the RAM cell unit 1 indicated by the RAM address decoder 2. Thus, the write circuit of the RAM operates very frequently.

As described above, in the single-chip microcomputer configured according to the present invention, the program stored in the ROM is always read into the RAM and the BT screening is performed, so that the write operation of the RAM is frequently performed during the dynamic BT. That is, effective dynamic BT can be performed regardless of the program stored in the ROM.

[Brief description of drawings]

FIG. 1 is a block diagram showing a configuration of a RAM of a single-chip microcomputer constructed according to the present invention, FIG. 2 is a block diagram showing a basic configuration of a single-chip microcomputer, and FIG. FIG. 6 is a block diagram showing a configuration of a RAM of a conventional single-chip microcomputer. [Main reference numbers] 1,31 …… RAM cell, 2,32 …… RAM address decoder, 3,33 …… Write circuit, 4,34 …… Read circuit, 5,25,35 …… Internal data bus, 6,9 ... OR gate, 7,8,10,11,36,37 ... AND gate, 21 ... CPU, 22 ... RAM, 23 ... ROM, 24 ... I / O circuit

Claims (1)

[Claims] 1. A RAM comprising a read circuit and a write circuit, which is coupled to an internal bus, and a built-in ROM, which is coupled to the internal bus via a read circuit and stores an instruction, in accordance with a ROM read signal. A single-chip microcomputer that executes an operation of reading an instruction stored in a built-in ROM, wherein the RO signal is read by the read signal in a test mode.
A single-chip microcomputer comprising a control circuit for controlling to write the contents of the bus read from M into the RAM.