JPS6488644A - Single chip microcomputer - Google Patents

Single chip microcomputer

Info

Publication number
JPS6488644A
JPS6488644A JP62245667A JP24566787A JPS6488644A JP S6488644 A JPS6488644 A JP S6488644A JP 62245667 A JP62245667 A JP 62245667A JP 24566787 A JP24566787 A JP 24566787A JP S6488644 A JPS6488644 A JP S6488644A
Authority
JP
Japan
Prior art keywords
ram
rom
circuit
content
comes
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP62245667A
Other languages
Japanese (ja)
Other versions
JPH069032B2 (en
Inventor
Tetsuo Kanai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP62245667A priority Critical patent/JPH069032B2/en
Publication of JPS6488644A publication Critical patent/JPS6488644A/en
Publication of JPH069032B2 publication Critical patent/JPH069032B2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Landscapes

  • Test And Diagnosis Of Digital Computers (AREA)
  • Microcomputers (AREA)

Abstract

PURPOSE:To execute effective dynamic BT irrespective of a program stored in a ROM by controlling so that the content on a bus read out from the ROM by a read signal is written in a RAM. CONSTITUTION:In the operation of dynamic BT, a TEST signal is shifted, from the external, to '1'. When the content in the ROM is read out on the data bus 5, a ROMRD signal comes in '1', and an output form an AND circuit 9 comes in '1'. Accordingly, an output from an OR circuit 7 comes in '1', hence a write circuit 3 turns active, and the data on the bus 5 is written in a RAM cell part 1 designated by a RAM address decoder 2. Like this, the write circuit 3 to write in the RAM writes therein extremely frequently. As a result, the RAM 1 can be operated during dynamic screening irrespective of the content in the incorporated ROM.
JP62245667A 1987-09-29 1987-09-29 Single chip microcomputer Expired - Lifetime JPH069032B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62245667A JPH069032B2 (en) 1987-09-29 1987-09-29 Single chip microcomputer

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62245667A JPH069032B2 (en) 1987-09-29 1987-09-29 Single chip microcomputer

Publications (2)

Publication Number Publication Date
JPS6488644A true JPS6488644A (en) 1989-04-03
JPH069032B2 JPH069032B2 (en) 1994-02-02

Family

ID=17137023

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62245667A Expired - Lifetime JPH069032B2 (en) 1987-09-29 1987-09-29 Single chip microcomputer

Country Status (1)

Country Link
JP (1) JPH069032B2 (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60254361A (en) * 1984-05-31 1985-12-16 Nec Corp Microcomputer
JPS6167148A (en) * 1984-09-10 1986-04-07 Nec Corp Microcomputer

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60254361A (en) * 1984-05-31 1985-12-16 Nec Corp Microcomputer
JPS6167148A (en) * 1984-09-10 1986-04-07 Nec Corp Microcomputer

Also Published As

Publication number Publication date
JPH069032B2 (en) 1994-02-02

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