JPS6426950A - Write protecting system for memory - Google Patents

Write protecting system for memory

Info

Publication number
JPS6426950A
JPS6426950A JP62184274A JP18427487A JPS6426950A JP S6426950 A JPS6426950 A JP S6426950A JP 62184274 A JP62184274 A JP 62184274A JP 18427487 A JP18427487 A JP 18427487A JP S6426950 A JPS6426950 A JP S6426950A
Authority
JP
Japan
Prior art keywords
memory
mpu
kept
output
0fff
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP62184274A
Other languages
Japanese (ja)
Inventor
Toshihiro Kimura
Ken Nishizuka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Construction Machinery Co Ltd
Original Assignee
Hitachi Construction Machinery Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Construction Machinery Co Ltd filed Critical Hitachi Construction Machinery Co Ltd
Priority to JP62184274A priority Critical patent/JPS6426950A/en
Publication of JPS6426950A publication Critical patent/JPS6426950A/en
Pending legal-status Critical Current

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  • Storage Device Security (AREA)

Abstract

PURPOSE:To avoid such a case where the data stored in a memory is destroyed by the runaway of an MPU by inhibiting the writing actions in response to an address signal and a switch circuit which can be externally operated. CONSTITUTION:When an MPU writes the addresses 0-0FFF while a switch 13 kept turned off, the output of an AND 7 is set at L and the output of an AND 10 is also set at L. Thus the output signal passed through an inverter 9 is set at H with the output signal of an AND 6 kept at H. As a result, the inverse of CS terminal of a RAM 1 is kept at H even though the MPU gives accesses to the addresses 0-0FFF. Thus no data could be written into the RAM 1.
JP62184274A 1987-07-23 1987-07-23 Write protecting system for memory Pending JPS6426950A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP62184274A JPS6426950A (en) 1987-07-23 1987-07-23 Write protecting system for memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP62184274A JPS6426950A (en) 1987-07-23 1987-07-23 Write protecting system for memory

Publications (1)

Publication Number Publication Date
JPS6426950A true JPS6426950A (en) 1989-01-30

Family

ID=16150451

Family Applications (1)

Application Number Title Priority Date Filing Date
JP62184274A Pending JPS6426950A (en) 1987-07-23 1987-07-23 Write protecting system for memory

Country Status (1)

Country Link
JP (1) JPS6426950A (en)

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