JPS6423343A - Programmable interruption signal generator - Google Patents

Programmable interruption signal generator

Info

Publication number
JPS6423343A
JPS6423343A JP18053587A JP18053587A JPS6423343A JP S6423343 A JPS6423343 A JP S6423343A JP 18053587 A JP18053587 A JP 18053587A JP 18053587 A JP18053587 A JP 18053587A JP S6423343 A JPS6423343 A JP S6423343A
Authority
JP
Japan
Prior art keywords
microprocessor
interruption
ram
data
written
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP18053587A
Other languages
Japanese (ja)
Inventor
Tetsuya Inoue
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP18053587A priority Critical patent/JPS6423343A/en
Publication of JPS6423343A publication Critical patent/JPS6423343A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/24—Handling requests for interconnection or transfer for access to input/output bus using interrupt

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)

Abstract

PURPOSE:To easily change the written data by applying an interruption level and a vector number to a microprocessor as the interruption signals. CONSTITUTION:An interruption signal is applied to a static RAM 6 via a selector 5 and the interruption level output is applied to a microprocessor 4 via an output bus OB. The microprocessor 4 receives the interruption level output and transmits a chip selection signal to read a vector number for execution of the interruption processing. When the contents of each register of the RAM 6 are changed, the selector 5 is switched toward the microprocessor 4. Then the address data is outputted to the RAM 6 from the microprocessor 4. The data to be written into each register is applied to the RAM 6 from the microprocessor 4 to perform the control when data are written and read out.
JP18053587A 1987-07-20 1987-07-20 Programmable interruption signal generator Pending JPS6423343A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18053587A JPS6423343A (en) 1987-07-20 1987-07-20 Programmable interruption signal generator

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18053587A JPS6423343A (en) 1987-07-20 1987-07-20 Programmable interruption signal generator

Publications (1)

Publication Number Publication Date
JPS6423343A true JPS6423343A (en) 1989-01-26

Family

ID=16084964

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18053587A Pending JPS6423343A (en) 1987-07-20 1987-07-20 Programmable interruption signal generator

Country Status (1)

Country Link
JP (1) JPS6423343A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6711641B2 (en) 2000-06-01 2004-03-23 Fujitsu Limited Operation processing apparatus

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6711641B2 (en) 2000-06-01 2004-03-23 Fujitsu Limited Operation processing apparatus

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