JPS5534751A - Information processing unit - Google Patents

Information processing unit

Info

Publication number
JPS5534751A
JPS5534751A JP10770778A JP10770778A JPS5534751A JP S5534751 A JPS5534751 A JP S5534751A JP 10770778 A JP10770778 A JP 10770778A JP 10770778 A JP10770778 A JP 10770778A JP S5534751 A JPS5534751 A JP S5534751A
Authority
JP
Japan
Prior art keywords
white
memories
processing unit
information
written
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10770778A
Other languages
Japanese (ja)
Inventor
Takahiko Yamada
Tatsuo Ushiki
Takafumi Saito
Yuzo Ishikawa
Hosaku Nakamura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Nippon Telegraph and Telephone Corp
Original Assignee
NEC Corp
Nippon Telegraph and Telephone Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Telegraph and Telephone Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP10770778A priority Critical patent/JPS5534751A/en
Publication of JPS5534751A publication Critical patent/JPS5534751A/en
Pending legal-status Critical Current

Links

Landscapes

  • Hardware Redundancy (AREA)
  • Exchange Systems With Centralized Control (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)

Abstract

PURPOSE: To shorten an access time to improve a processing speed by shortening signal line length between a processing unit and a white-system memory and limiting the read operation only to the white-system memory and performing information write for both system memories.
CONSTITUTION: In case that two processing units CC0 and CC1 execute the same program and perform a synchronous operation, they read out memory contents from white-system memories MM0 and MM1, which are connected with the shortest distance by signal lines 1 and 1', to execute the program. In case that information is written from one unit CC0 or CC1 to memories MM0 and MM1, the same instruction is executed synchronously by units CC0 and CC1 simultaneously, and the same information is written in both system memories MM0 and MM1.
COPYRIGHT: (C)1980,JPO&Japio
JP10770778A 1978-09-02 1978-09-02 Information processing unit Pending JPS5534751A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10770778A JPS5534751A (en) 1978-09-02 1978-09-02 Information processing unit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10770778A JPS5534751A (en) 1978-09-02 1978-09-02 Information processing unit

Publications (1)

Publication Number Publication Date
JPS5534751A true JPS5534751A (en) 1980-03-11

Family

ID=14465899

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10770778A Pending JPS5534751A (en) 1978-09-02 1978-09-02 Information processing unit

Country Status (1)

Country Link
JP (1) JPS5534751A (en)

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5160422A (en) * 1974-11-25 1976-05-26 Hitachi Ltd Fuairuno 2 jugakino hoshiki
JPS53104137A (en) * 1977-02-23 1978-09-11 Toshiba Corp Minicomputer composite system

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5160422A (en) * 1974-11-25 1976-05-26 Hitachi Ltd Fuairuno 2 jugakino hoshiki
JPS53104137A (en) * 1977-02-23 1978-09-11 Toshiba Corp Minicomputer composite system

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