JPS5672745A - Priority circuit - Google Patents

Priority circuit

Info

Publication number
JPS5672745A
JPS5672745A JP14983479A JP14983479A JPS5672745A JP S5672745 A JPS5672745 A JP S5672745A JP 14983479 A JP14983479 A JP 14983479A JP 14983479 A JP14983479 A JP 14983479A JP S5672745 A JPS5672745 A JP S5672745A
Authority
JP
Japan
Prior art keywords
circuit
priority level
priority
memory circuit
inputs
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP14983479A
Other languages
Japanese (ja)
Other versions
JPS6315620B2 (en
Inventor
Hisao Nagata
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP14983479A priority Critical patent/JPS5672745A/en
Publication of JPS5672745A publication Critical patent/JPS5672745A/en
Publication of JPS6315620B2 publication Critical patent/JPS6315620B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Logic Circuits (AREA)
  • Bus Control (AREA)

Abstract

PURPOSE: To make it possible to change a priority level easily without modifying wiring, etc., by making it possible to set a different priority level by rewriting a truth table that corresponds to the priority level of a logic circuit part that deciding the priority level.
CONSTITUTION: Memory circuit 20" is stored with the truth table which outputs the priority level that corresponds to that of an input signal and to this memory circuit 20", address change-over circuit 40" is connected. To this circuit 40", read-write control signal 18" is applied to select signals of priority inputs 1"W3" sides or address signals 31"W33", which are led to the address inputs of memory unit 20". When signal 18" is in write mode, the output of inverter 19" is held at "1" to apply address signals 31"W33" to memory circuit 20" via circuit 40" and when in read mode, priority inputs 1"W3" are applied to memory circuit 20" via circuit 40" to make it possible to rewrite the truth table in memory circuit 20", so that priority levels from output terminals 11"W13" will be changed easily without modifying wiring, etc.
COPYRIGHT: (C)1981,JPO&Japio
JP14983479A 1979-11-19 1979-11-19 Priority circuit Granted JPS5672745A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP14983479A JPS5672745A (en) 1979-11-19 1979-11-19 Priority circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP14983479A JPS5672745A (en) 1979-11-19 1979-11-19 Priority circuit

Publications (2)

Publication Number Publication Date
JPS5672745A true JPS5672745A (en) 1981-06-17
JPS6315620B2 JPS6315620B2 (en) 1988-04-05

Family

ID=15483674

Family Applications (1)

Application Number Title Priority Date Filing Date
JP14983479A Granted JPS5672745A (en) 1979-11-19 1979-11-19 Priority circuit

Country Status (1)

Country Link
JP (1) JPS5672745A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6478329A (en) * 1987-09-19 1989-03-23 Fujitsu Ltd Interruption controller
JPH01222342A (en) * 1988-03-02 1989-09-05 Pfu Ltd Data processor
JPH02247736A (en) * 1989-03-22 1990-10-03 Sharp Corp Mask programmable interruption controller

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6478329A (en) * 1987-09-19 1989-03-23 Fujitsu Ltd Interruption controller
JPH01222342A (en) * 1988-03-02 1989-09-05 Pfu Ltd Data processor
JPH02247736A (en) * 1989-03-22 1990-10-03 Sharp Corp Mask programmable interruption controller

Also Published As

Publication number Publication date
JPS6315620B2 (en) 1988-04-05

Similar Documents

Publication Publication Date Title
JPS55128641A (en) Controlling system for vehicle
CA2038162A1 (en) Programmable connector
JPS5345120A (en) Video special effect device
DE69610824D1 (en) READING AMPLIFIER WITH PULL-UP CIRCUIT FOR ACCELERATING THE LOGICAL RULE OF OUTPUT DATA
JPS648580A (en) Memory device for electronic equipment
JPS5672745A (en) Priority circuit
JPS5710853A (en) Memory device
JPS5748127A (en) Data processor
JPS56101247A (en) Audio output device
JPS57100691A (en) Memory access control system
JPS5730196A (en) Information processor
JPS56149607A (en) Arithmetic controller
KR940008120Y1 (en) Memory controller for display
JPS5699550A (en) Information processing unit
JPS6459540A (en) Microcomputer
JPS54111229A (en) Input control system
JPS5562592A (en) Non-volatile semiconductor memory control circuit
JPS5769413A (en) Programmable logic controller
FR2417140A1 (en) Sequential calculator with PROM - has 8-bit instruction cope with first two bits determining task to be selected for execution from four possible tasks
ATE89091T1 (en) MULTIVALUE ALE.
DE3887290D1 (en) Circuit arrangement for the safety-effective determination of the state of an output memory stage.
KR940001160A (en) Signal processing structure to preselect memory address data
JPS5447538A (en) Channel device
JPS644980A (en) Data reproducing device
JPS5525109A (en) Logic circuit