JPS5672745A - Priority circuit - Google Patents
Priority circuitInfo
- Publication number
- JPS5672745A JPS5672745A JP14983479A JP14983479A JPS5672745A JP S5672745 A JPS5672745 A JP S5672745A JP 14983479 A JP14983479 A JP 14983479A JP 14983479 A JP14983479 A JP 14983479A JP S5672745 A JPS5672745 A JP S5672745A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- priority level
- priority
- memory circuit
- inputs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Logic Circuits (AREA)
- Bus Control (AREA)
Abstract
PURPOSE: To make it possible to change a priority level easily without modifying wiring, etc., by making it possible to set a different priority level by rewriting a truth table that corresponds to the priority level of a logic circuit part that deciding the priority level.
CONSTITUTION: Memory circuit 20" is stored with the truth table which outputs the priority level that corresponds to that of an input signal and to this memory circuit 20", address change-over circuit 40" is connected. To this circuit 40", read-write control signal 18" is applied to select signals of priority inputs 1"W3" sides or address signals 31"W33", which are led to the address inputs of memory unit 20". When signal 18" is in write mode, the output of inverter 19" is held at "1" to apply address signals 31"W33" to memory circuit 20" via circuit 40" and when in read mode, priority inputs 1"W3" are applied to memory circuit 20" via circuit 40" to make it possible to rewrite the truth table in memory circuit 20", so that priority levels from output terminals 11"W13" will be changed easily without modifying wiring, etc.
COPYRIGHT: (C)1981,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14983479A JPS5672745A (en) | 1979-11-19 | 1979-11-19 | Priority circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP14983479A JPS5672745A (en) | 1979-11-19 | 1979-11-19 | Priority circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5672745A true JPS5672745A (en) | 1981-06-17 |
JPS6315620B2 JPS6315620B2 (en) | 1988-04-05 |
Family
ID=15483674
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP14983479A Granted JPS5672745A (en) | 1979-11-19 | 1979-11-19 | Priority circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5672745A (en) |
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6478329A (en) * | 1987-09-19 | 1989-03-23 | Fujitsu Ltd | Interruption controller |
JPH01222342A (en) * | 1988-03-02 | 1989-09-05 | Pfu Ltd | Data processor |
JPH02247736A (en) * | 1989-03-22 | 1990-10-03 | Sharp Corp | Mask programmable interruption controller |
-
1979
- 1979-11-19 JP JP14983479A patent/JPS5672745A/en active Granted
Cited By (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS6478329A (en) * | 1987-09-19 | 1989-03-23 | Fujitsu Ltd | Interruption controller |
JPH01222342A (en) * | 1988-03-02 | 1989-09-05 | Pfu Ltd | Data processor |
JPH02247736A (en) * | 1989-03-22 | 1990-10-03 | Sharp Corp | Mask programmable interruption controller |
Also Published As
Publication number | Publication date |
---|---|
JPS6315620B2 (en) | 1988-04-05 |
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