FR2417140A1 - Sequential calculator with PROM - has 8-bit instruction cope with first two bits determining task to be selected for execution from four possible tasks - Google Patents

Sequential calculator with PROM - has 8-bit instruction cope with first two bits determining task to be selected for execution from four possible tasks

Info

Publication number
FR2417140A1
FR2417140A1 FR7803864A FR7803864A FR2417140A1 FR 2417140 A1 FR2417140 A1 FR 2417140A1 FR 7803864 A FR7803864 A FR 7803864A FR 7803864 A FR7803864 A FR 7803864A FR 2417140 A1 FR2417140 A1 FR 2417140A1
Authority
FR
France
Prior art keywords
memory
decoder
prom
cope
execution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
FR7803864A
Other languages
French (fr)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
REUFLET JEAN CLAUDE
Original Assignee
REUFLET JEAN CLAUDE
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by REUFLET JEAN CLAUDE filed Critical REUFLET JEAN CLAUDE
Priority to FR7803864A priority Critical patent/FR2417140A1/en
Publication of FR2417140A1 publication Critical patent/FR2417140A1/en
Withdrawn legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G06F1/3234—Power saving characterised by the action undertaken
    • G06F1/325—Power saving in peripheral device
    • G06F1/3275—Power saving in memory, e.g. RAM, cache
    • G—PHYSICS
    • G05—CONTROLLING; REGULATING
    • G05B—CONTROL OR REGULATING SYSTEMS IN GENERAL; FUNCTIONAL ELEMENTS OF SUCH SYSTEMS; MONITORING OR TESTING ARRANGEMENTS FOR SUCH SYSTEMS OR ELEMENTS
    • G05B19/00—Programme-control systems
    • G05B19/02—Programme-control systems electric
    • G05B19/04—Programme control other than numerical control, i.e. in sequence controllers or logic controllers
    • G05B19/045—Programme control other than numerical control, i.e. in sequence controllers or logic controllers using logic state machines, consisting only of a memory or a programmable logic device containing the logic for the controlled machine and in which the state of its outputs is dependent on the state of its inputs or part of its own output states, e.g. binary decision controllers, finite state controllers
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F1/00—Details not covered by groups G06F3/00 - G06F13/00 and G06F21/00
    • G06F1/26—Power supply means, e.g. regulation thereof
    • G06F1/32—Means for saving power
    • G06F1/3203—Power management, i.e. event-based initiation of a power-saving mode
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/22—Microcontrol or microprogram arrangements
    • G06F9/26—Address formation of the next micro-instruction ; Microprogram storage or retrieval arrangements
    • G06F9/262—Arrangements for next microinstruction selection
    • G06F9/264—Microinstruction selection based on results of processing
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y02—TECHNOLOGIES OR APPLICATIONS FOR MITIGATION OR ADAPTATION AGAINST CLIMATE CHANGE
    • Y02D—CLIMATE CHANGE MITIGATION TECHNOLOGIES IN INFORMATION AND COMMUNICATION TECHNOLOGIES [ICT], I.E. INFORMATION AND COMMUNICATION TECHNOLOGIES AIMING AT THE REDUCTION OF THEIR OWN ENERGY USE
    • Y02D10/00—Energy efficient computing, e.g. low power processors, power management or thermal management

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • Software Systems (AREA)
  • Automation & Control Theory (AREA)
  • Executing Machine-Instructions (AREA)

Abstract

The sequential calculator has a programmable memory in which is stored in coded binary form a certain number of instructions. Each instruction defines a task to be executed and the address of the following instruction. A first decoder is connected to the memory, this decoder selects a determined number of variables which are being supervised. A record decoder (7) connected to the memory sends selectively a control signal towards a determined number of control elements. A third 'operation' decoder (8) connected to the memory and to the other decoders controls as a function of the structure of each instruction from the memory the task to be executed. An address circuit connected to the memory and operation decoder gives the address of the following instruction to the memory.
FR7803864A 1978-02-10 1978-02-10 Sequential calculator with PROM - has 8-bit instruction cope with first two bits determining task to be selected for execution from four possible tasks Withdrawn FR2417140A1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
FR7803864A FR2417140A1 (en) 1978-02-10 1978-02-10 Sequential calculator with PROM - has 8-bit instruction cope with first two bits determining task to be selected for execution from four possible tasks

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR7803864A FR2417140A1 (en) 1978-02-10 1978-02-10 Sequential calculator with PROM - has 8-bit instruction cope with first two bits determining task to be selected for execution from four possible tasks

Publications (1)

Publication Number Publication Date
FR2417140A1 true FR2417140A1 (en) 1979-09-07

Family

ID=9204470

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7803864A Withdrawn FR2417140A1 (en) 1978-02-10 1978-02-10 Sequential calculator with PROM - has 8-bit instruction cope with first two bits determining task to be selected for execution from four possible tasks

Country Status (1)

Country Link
FR (1) FR2417140A1 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0238125A2 (en) * 1986-03-21 1987-09-23 Advanced Micro Devices, Inc. Programmable sequencer
FR2687809A3 (en) * 1992-02-21 1993-08-27 Bernard Roux Device for optimising the operating autonomy of a microprocessor

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0238125A2 (en) * 1986-03-21 1987-09-23 Advanced Micro Devices, Inc. Programmable sequencer
EP0238125A3 (en) * 1986-03-21 1989-03-15 Advanced Micro Devices, Inc. Programmable sequencer
FR2687809A3 (en) * 1992-02-21 1993-08-27 Bernard Roux Device for optimising the operating autonomy of a microprocessor

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Legal Events

Date Code Title Description
ST Notification of lapse