JPS6315620B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a priority circuit used in electronic computers and the like. Conventional priority input order determination circuit in which when a signal is applied to multiple input terminals each having a different priority order, the signal is output to the output terminal corresponding to the input terminal with the highest order priority. An example is shown in FIG. When the priorities of three input terminals 1, 2, and 3 having mutually different priorities are 1>2>3, the input terminals 1, 2, and 3 and the output terminals 11, 12, and 13 corresponding to each input terminal The truth table of is as follows.

[Table] The x marks shown at input 2 and input 3 indicate that the logic holds true for either logic 1 or 0. It can be seen that if the input signal with a higher priority is logic 1, the output is determined regardless of the signal with a lower priority. In this example, the input priority is 1>2>3, so if input 1 is logic 1, output 11 corresponding to 1 is logic 1, but other logic outputs 12, 1
3 becomes logical 0. In the circuit of Figure 1, the priorities are 1>2>3, and the highest priority input 1
When is logic 1, output 11 is logic 1, but since logic 0 from the inverted output 14 of input 1 is added to the inputs of other AND gates 12 and 13, AND gate output 12=13=logic 0. In the priority input order determination circuit shown in FIG. 1, a predetermined input signal may be connected to the input terminal whose priority order has been determined. However, on the other hand, if you try to change the priority order of input signals, for example, change the priority order from 1>2>3 to 2>1>
3, the connections must be changed as shown in Figure 2, and it is virtually impossible to change the wiring on the printed circuit board that carries electronic components, and the input terminal wires of the printed circuit board must be changed. It is very complicated to change. An object of the present invention is to provide a priority circuit that can arbitrarily set the priority order and output a judgment output according to the predetermined priority order even if a plurality of input signals with different priority orders are input at the same time. It is to provide. According to the present invention, a combination of n (n≧2) priority input signals is applied as an address, and a storage device outputs n judgment output signals in response to the combination, and a circuit for writing a truth table according to the priority order of the priority input signals, and N pieces of information stored at addresses specified by the combination of the priority input signals applied to the storage device. A priority circuit is obtained in which the above-described determination output signal is outputted as the determination output signal. The truth table of the storage device mentioned above can be rewritten arbitrarily, and even if multiple input signals with different priorities are applied to the storage device at the same time, only the signal determined to have the highest priority among them will be true. Since the judgment output is output according to the value table, it is possible to allow multiple input signals to exist at the same time and to judge them correctly. Next, embodiments of the present invention will be described. FIG. 3 is a block diagram showing one embodiment of the present invention. The address switching circuit 40'' of the storage device 20'', which will be described later, selects priority inputs 1'' to 1'' by the read/write control signal (hereinafter referred to as R/W signal) 18'' of the storage device 20'', which will be described later.
3'' side or the write address signals 31'' to 33'' side are selected and transmitted to the address input of the storage device 20''. R/W signal 18'' is read (=logic 1)
When , priority input signals 1'' to 3'' are set to 4
7'' to 49'' → The selected signal is added to the address input of the storage device 20'' through OR gates 41'' to 43'', and a truth table according to the priority order of priority input signals 1'' to 3'' is stored. The contents of the storage device 20'' are read out, and the determination outputs of the priority input signals 11'' to 13'' are output to 11'' to 13''. R/W signal 18″
When is written (=logic 0), the inverter
19″ output becomes logic 1, address switching circuit 4
0'' converts the write address signals 31'' to 33'' to AND gates 44'' to 46'' → OR gates 41'' to 4.
3'' to the address input of the storage device 20''. At this time, since the R/W signal 18'' is for writing to the storage device 20'', the write address signal 3
Write data 21'' to 23'' are written to addresses controlled by 1'' to 33''. To obtain the same priority determination output as in Figs. 1 and 2, Fig. 4,
The data shown in the truth table as shown in FIG. 5 may be written into the storage device. When the truth table of Fig. 4 is stored, if input 1'' is logic 1, output 31'' = 1, output 32'', regardless of the combination of other inputs 2'' and 3''. = 0, output 33'' = 0, and it can be seen that the same judgment output as the circuit in FIG. 1 can be obtained with other input combinations. In this way, by changing the truth table for priority determination stored in the storage device, it is possible to easily change the priority order of input signals. As is clear from the above explanation, by configuring the priority order determination circuit with a rewritable storage device, the priority order can be changed easily and quickly without changing wiring or the like.

[Brief explanation of the drawing]

1 and 2 are diagrams showing a conventional priority circuit, FIG. 3 is a circuit diagram showing an embodiment of the present invention, and FIGS. 4 and 5 are diagrams showing an example of the operation of the circuit in FIG. 3. It is. 1, 2, 3...input terminals, 11-13...output terminals.

Claims (1)

[Claims] 1 A storage device to which a combination of n (n≧2) priority input signals is applied as an address and outputs n determination output signals in response; a circuit for writing a truth table according to the priority order, and N is stored at an address specified by a combination of the priority input signals applied to the storage device.
A priority circuit characterized in that information on the number of items is outputted as the determination output signal.