JPH02230481A - Microcomputer - Google Patents

Abstract

PURPOSE:To select a microcomputer with a large number of port terminals or a microcomputer executable external access at high speed by designating whether data bus is shared with a low-order address signal or the data bus and a low-order address line are dedicated, respectively by a control signal. CONSTITUTION:The device is constituted by providing a first selection means 7 which selects first terminal groups P0/A0-P7/A7 as the port terminals when the control signal from a control terminal 4 is set at a first state, and second terminal groups DB0/A0-DB7/A7 as the terminals sharing an address and data, and a second selection means 6 which selects the first terminal groups P0/A0-P7/A7 as address terminals and the second terminal groups DB0/A0-DB7/ A7 as data terminals when the control signal is set at a second state. Thereby, it is possible to easily select the function of the microcomputer with the large number of port terminals or that of the microcomputer executable the external access at high speed.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a microcomputer (hereinafter referred to as a microcomputer) constructed of a semiconductor integrated circuit, and particularly relates to a function for accessing a memory device located outside the microcomputer. The present invention relates to a microcomputer having a

[Conventional technology]

A microcomputer that can access an external memory device requires an address signal for addressing the memory device and a data bus for reading data from or writing data to the memory device.

Conventionally, microcontrollers intended for high-speed external access have dedicated data bus terminals and address terminals. That is, the external memory device is accessed by outputting an address signal using the dedicated address terminal, and data is exchanged with the memory device via the dedicated data bus terminal. With such a configuration, the access cycle time is short and high speed is possible.

However, a one-chip microcomputer has a limited number of terminals. Therefore, if the terminals are dedicated as described above, the number of terminals that can be used as ports will be limited. Therefore, in microcomputers that place more importance on the number of terminals that can be used as ports than on speeding up, a system is used in which data bus terminals and address terminals are shared. That is, at the first timing, the data and address terminal is used as the address terminal to output address information, and at the second timing, the data and address terminal is used as the data terminal to send and receive data. With such a configuration, it is possible to increase the number of terminals used as ports since the terminals are used both as data bus terminals and address terminals.

[Problem to be solved by the invention]

In this way, two types of microcontrollers are used depending on the system specifications and purpose of use. Therefore, each microcomputer must be designed and evaluated separately, which poses a problem in terms of cost.

An object of the present invention is to provide a microcomputer that can easily select functions of a microcomputer with a large number of port terminals and functions of a microcomputer that can perform external access at high speed.

[Means to solve the problem]

The microcontroller of the present invention includes a first selection means that selects a first terminal group as port terminals and a second terminal group as address and data terminals when the control signal is in the first state; is in the second state, the first terminal group is selected as address terminals and the second terminal group is selected as data terminals.

〔Example〕

Next, the present invention will be explained with reference to the drawings.

FIGS. 1(a) to 1(c) are a block diagram and a timing diagram for explaining one embodiment of the present invention.

The control terminal 4 is a terminal for inputting a high level or loge level, and the input signal of this terminal is input to an AND circuit 5.
Controls the selection circuit 6 that specifies whether to select the data bus or the data bus and address signals AO-A7 in a time-sharing manner, and selects the boat input/output signals PO-P7 or the address signals AO to A7. Controls the shift selection circuit 7.

The input/output signals PO-P7 are connected to the port function block 8. Address signals AO to An are output from address generation circuit 9, and address signals AO to A7
are input to the selection circuits 6 and 7, and the address signals A8 to A
n and are output from terminals A8 to An, respectively. The other input of the AND circuit 5 is an address latch signal output from the latch signal generation circuit 10, and the other input of the AND circuit 5
The output of is output from the ADL terminal.

Next, the operation of the present invention will be explained in detail. First, when the control terminal 4 is set to a high level, the AND circuit 5 transmits the output of the latch signal generation circuit 10, and outputs an address latch signal from the ADL terminal at a predetermined timing. The selection circuit 6 selects the address AO of the terminals DBO/AO to DB7/A7 according to the timings tA and tE shown in FIG. 1(b).
~A7 or the data bus is selected in time division. That is, t
At A, addresses AO to A7 are outputted via the DBO/AO-DB77A7 terminal, and at tB, it is connected to the data bus and input/output of data is executed. On the other hand, the selection circuit 7 selects the outputs PO to P7 of the port function block 8, and selects the outputs PO to P7 of the port function block 8.
The /AO-Pγ/AO terminal functions as port 1. The A8-An terminals output upper address signals A8-An. Therefore, when the signal from the control terminal 4 is high, the DBO/AO to DB7/A7 terminals select the address terminal and the data bus terminal in time division, and the DBO/AO to P7/A7 terminals
A. 7 is a microcomputer configuration that emphasizes the number of port terminals and has port 1/close functions.

Next, when the control terminal 4 is set to low level, the AND circuit 5 becomes low level and no address latch signal is output. (Incidentally, the ADL terminal can also be used to operate as a port.) At this time, the selection circuit 6 selects only the data bus and connects DBO/AO to DB7/A7.
The terminal operates as a data bus terminal. Also, the selection circuit 7
selects address AO~A7 and PO/AO~P7/
The A7 terminal outputs address AO-A7. A8~A
The n terminal outputs the upper address signal regardless of the control signal 4. Therefore, when the signal from control terminal 4 is low, the terminals of DBO/AO-DB7/A7 operate as a data bus, and PO/AO to P7/A7 operate as address terminals. Emphasis is placed on speeding up external access. The configuration of the microcomputer is as follows.

FIG. 2 shows another embodiment of the invention. In FIG. 2, the same circuits and terminals as in FIG. 1 are given the same names. The difference from FIG. 1 is that the control terminal 4 is not required, and the microcomputer 1 is configured so that the control signal 11 can be set to a high level or a p-level. Specifically, the control signal 11 is constructed of a microcomputer integrated circuit, but two types of microcomputers may be manufactured by fixing the control signal 11 to a high level or a low level during the manufacture of the integrated circuit. Since this embodiment does not require a control terminal, it has the advantage that the terminal can be used as a port terminal and the functionality of the microcomputer can be further improved.

〔Effect of the invention〕

As explained above, the present invention is configured so that it can be specified by a control signal whether to share the data bus and lower address signals or to dedicate the data bus and lower address lines, thereby reducing the number of port terminals. This has the effect of allowing you to select a microcomputer with a large number of devices or a microcomputer that can perform external access at high speed.

In particular, since microcontrollers are realized as integrated circuits, by simply developing one type of microcontroller according to the present invention, a microcontroller with a large number of port terminals or a microcontroller that can perform external access at high speed can be realized. Another benefit is that the microcontroller can be designed and evaluated only once, reducing development costs.

[Brief explanation of the drawing]

FIG. 1(a) is a block diagram for explaining one embodiment of the microcomputer of the present invention, and FIG. 1(b) and (C) are FIG.
FIG. 2 is a block diagram of a microcomputer for explaining another embodiment of the present invention. 1...Microcomputer, 2...External memory device, AO~An...Address terminal. DBO~D
B7...Data bus terminal, 3...Latch circuit, 4...Control terminal, 5...AND circuit, 6,7... Selection circuit, 8...
Port function block, 9...Address generation circuit, 1
0... Latch signal generation circuit, 1]...
Control signal, ADL...Address latch signal output terminal, DBO/AO to DB77A7...Dual bus and address signal terminal, P O/A O-P
7/A 7... Port function terminal and address signal terminal. Agent Patent Attorney Susumu Uchihara

Claims (1)

[Claims] In a microcomputer having a first terminal group and a second terminal group, when the control signal is in the first state, the first
a first selection means for selecting the terminal group as boat terminals and the second terminal group as address and data dual-purpose terminals; and when the control signal is in a second state, the first terminal group a second selection means for selecting the second group of terminals as address terminals and selecting the second group of terminals as data bus terminals.