JPS57211651A - Patch system - Google Patents

Patch system

Info

Publication number
JPS57211651A
JPS57211651A JP56095989A JP9598981A JPS57211651A JP S57211651 A JPS57211651 A JP S57211651A JP 56095989 A JP56095989 A JP 56095989A JP 9598981 A JP9598981 A JP 9598981A JP S57211651 A JPS57211651 A JP S57211651A
Authority
JP
Japan
Prior art keywords
address
patch
ram
skip
specific
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP56095989A
Other languages
Japanese (ja)
Inventor
Kinya Maruko
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp, Tokyo Shibaura Electric Co Ltd filed Critical Toshiba Corp
Priority to JP56095989A priority Critical patent/JPS57211651A/en
Publication of JPS57211651A publication Critical patent/JPS57211651A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F8/00—Arrangements for software engineering
    • G06F8/60—Software deployment
    • G06F8/65—Updates
    • G06F8/66—Updates of program code stored in read-only memory [ROM]
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/32—Address formation of the next instruction, e.g. by incrementing the instruction counter
    • G06F9/322—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address
    • G06F9/328—Address formation of the next instruction, e.g. by incrementing the instruction counter for non-sequential address for runtime instruction patching

Abstract

PURPOSE:To apply a patch easily to an ROM control system having no patch, by outputting the same address as a specific address from a CPU and activating a patch processing enable signal to perform the processing of a skip address. CONSTITUTION:Contents of a patch are read out from an external storage device and are stored in an address of an RAM 5. A skip address and a specific address are stored in registers 6 and 7 respectively. An enable signal for the patch processing is activated. A CPU 1 sends the same address as the specific address to an address patch circuit 2 and activates an AIR. The same address as the specific address is taken into a comparator 10, and the specific address is inputted to the comparator 10 through a selector 9. Since both addresses are equal as the result of comparison, a low-level signal is applied to a selector 13, and the skip address is sent to the RAM 5. Thus, a patch program is read out from the RAM 5.
JP56095989A 1981-06-23 1981-06-23 Patch system Pending JPS57211651A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP56095989A JPS57211651A (en) 1981-06-23 1981-06-23 Patch system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP56095989A JPS57211651A (en) 1981-06-23 1981-06-23 Patch system

Publications (1)

Publication Number Publication Date
JPS57211651A true JPS57211651A (en) 1982-12-25

Family

ID=14152535

Family Applications (1)

Application Number Title Priority Date Filing Date
JP56095989A Pending JPS57211651A (en) 1981-06-23 1981-06-23 Patch system

Country Status (1)

Country Link
JP (1) JPS57211651A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6011945A (en) * 1983-07-01 1985-01-22 Matsushita Electric Ind Co Ltd Debugging device
EP0514806A2 (en) * 1991-05-23 1992-11-25 Sony Corporation An electronics apparatus
US5454100A (en) * 1992-09-18 1995-09-26 Sony Corporation Electronic apparatus
US5619678A (en) * 1992-09-19 1997-04-08 Sony Corporation Electronic device for correction of ROM data with a parameter for calculation of position of correction data
US5623665A (en) * 1992-01-13 1997-04-22 Sony Corporation Electronic apparatus for patching a read-only memory
US5731972A (en) * 1992-09-19 1998-03-24 Sony Corporation Electronic apparatus which inhibits control of certain objects during initialization processing
US6128751A (en) * 1992-01-24 2000-10-03 Sony Corporation Electronic apparatus and method for patching a fixed information

Cited By (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6011945A (en) * 1983-07-01 1985-01-22 Matsushita Electric Ind Co Ltd Debugging device
JPH0432418B2 (en) * 1983-07-01 1992-05-29
EP0514806A2 (en) * 1991-05-23 1992-11-25 Sony Corporation An electronics apparatus
US6237120B1 (en) 1991-05-23 2001-05-22 Sony Corporation Program patching of a ROM
US5623665A (en) * 1992-01-13 1997-04-22 Sony Corporation Electronic apparatus for patching a read-only memory
US6128751A (en) * 1992-01-24 2000-10-03 Sony Corporation Electronic apparatus and method for patching a fixed information
US5454100A (en) * 1992-09-18 1995-09-26 Sony Corporation Electronic apparatus
US5619678A (en) * 1992-09-19 1997-04-08 Sony Corporation Electronic device for correction of ROM data with a parameter for calculation of position of correction data
US5731972A (en) * 1992-09-19 1998-03-24 Sony Corporation Electronic apparatus which inhibits control of certain objects during initialization processing

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