JPS6012660B2 - memory device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to memory devices, and more particularly to memory devices including readable and writable memory elements.

Conventional readable and writable memory (hereinafter referred to as RAM)
The RAM element mounted on the board can be programmed during program development.

When a program command is written to this RAM group and then a program back is executed, the central processing unit CPU may execute a processing procedure different from the processing procedure predetermined by the program. This is mainly caused by the addition of write signals due to noise or programming errors, but it is said that even the regular program data written in the RAM used as the program storage area is rewritten due to this noise or programming errors. There were drawbacks. An object of the present invention is to provide a RAM device in which program instructions written in a RAM element are not rewritten to incorrect program information due to noise or programming errors.

The present invention provides a control circuit that unselects a RAM chip on a memory board, and provides a non-selection signal to the RAM chip from this control circuit, thereby preventing data from being written to the RAM chip except during predetermined write times. configured to do so.

According to the present invention, data writing to the RAM is prohibited by a non-selection signal from the control circuit outside of a predetermined period, so that a legitimate program written to the RAM during a predetermined period may be affected by noise, program errors, etc. will not be rewritten with incorrect information.

Hereinafter, the present invention will be explained in more detail with reference to the drawings.

FIG. 1 is a block diagram showing a part of a memory device showing one embodiment of the present invention.

The RAM chip 4 on the memory board has an input/output terminal k for a data bus DS and an input terminal i for an address bus AB.A write signal S2 is input to the key 1, and a chip is input from the chip select terminal h of the decoder 3 to the terminal i. A select signal is input. On the other hand, the decoder 3 has the upper bit AB' (in this embodiment, the upper 2 bits) of the address signal for chip selection.
bit) is input to terminals f and g. AN to terminal e
A decoder control signal is input from the output terminal m of the D gate 2, and the input terminals c and d of the AND gate 2 are connected to the output terminal b of the inverter 1 and the data read signal S. A voltage Z of 15 V is applied to the input terminal a of the inverter 1 via a resistor R, and is grounded via a switch SW. According to this embodiment with such a configuration, when the switch SW is in the OFF state, the input terminal a of the inverter is pulled up to 15V via the resistor R, so a 2 "1" level is input, and the output of the inverter 1 is A "0" level is output from the terminal b, and this signal enters one input terminal c of the two-input AND gate 2.

That is, the "0" level is outputted to the output terminal m of the two-input AND gate 2, and this signal enters the chip selection state e of the decoder 32, so that the decoder 3 becomes active. On the other hand, the input terminal c of the 2-input AND gate 2 is connected to the switch SW.
As long as it is OFF, it is at the "0" level, so it is always at the "0" level regardless of whether the data read signal S at the other input terminal d of the two-input AND gate 2 is "0" or "1". Since the "0" level is output to the terminal m, the decoder 3 is in the active state. The input terminals f and g of the decoder 3 in the active state receive upper bit address signals AB, respectively.
' is input, and by the combination of level 3 of the input signals, the "0" level is output from the chip select signal output terminal h of one location designated by the upper address signal AB' among the plurality of output terminals of the decoder 3 of the RAM 4. The signal is input to the chip select terminal j, and the RAM chip 4 becomes active. R.A.
Address information output from the CPU is input to the M address 4 input terminal i through the address bus AB, and the RAM
Data is input to the data input terminal h of the RAM 4 via the data bus DB depending on the level state of the data write signal S2 input to the input/output control terminal 1 of the RAM 4 (in this embodiment, it is at the "0" level). Ru. On the other hand, when the switch SW is turned on, the input terminal a of the inverter 1 goes to the "0" level, so the isoverter output terminal b goes to the "1" level and the 2
It enters the input terminal C of the input AND gate 2.

At this time, the data read signal S. is input, (read signal CPU is RA
It is assumed that the signal is at the "0" level only when reading the contents of M4, and is at the "1" level during operations other than 0.
) AND gate output terminal m is at “0” level only when the CPU reads the inside of the memory, and is “1” at other times.
” level signal is output and input to chip select terminal e of decoder 3. Chip select terminal e is “1”
At the time of level, that is, except during the data read period, the decoder 3 is in an inhibited state, and the "1" level is input from the decoder output terminal h to the chip select terminal i of the RAM 4, and the RA
M memory 4 becomes prohibited. Also read signal “0”
When the level is input to the terminal d, the "0" level is output to the chip select terminal e of the decoder 3, the decoder 3 becomes active, and the signal specified by the upper bit AB' of the address signal is output from the decoder output terminal h. The chip select signal (0" level signal) is output to the RAM chip 4 to be selected, and the chip select terminal i of the RAM memory 4 is set to "0".
” level, RAM4 becomes active, and the data stored at the address specified by the address signal AB is read out through the data bus DB.The input control terminal 1 of RAM4 is set only when the CPU writes data to RAM4. “0” level is output during other operations.
A “1” level signal S2 is input. This signal is “0”
Even so, when the chip select terminal i of the RAM 4 is at the "1" level, that is, when the switch is in the ON state and the read signal S is at the "1" level, the RAM chip 4 is in the inhibited state, so data cannot be processed. Writing is prohibited. Therefore, at this time, the RAM chip 4 becomes read-only. As described above, according to this embodiment, data can be written to the RAM chip 4 only when the switch SW is turned FF, and when the switch SW is turned on, the RAM chip 4 operates as a read-only memory.

Therefore, writing of erroneous data to the RAM chip due to noise generated during program debugging, program errors, etc. can be prevented by turning the switch OFF. In this embodiment, a hand-held switch is used as the switch, but a gate circuit that is turned off only when data is being written under program control may also be used.

Further, in this embodiment, the RAM chip is disabled by controlling the chip select signal of the decoder, but a signal may be added to directly disable the RAM chip without going through the decoder. Furthermore, if the RAM chip and control circuit of the present invention are used as a storage area for programs and data during program development in a microcomputer system as an application of the present invention, the stored programs will be destroyed due to malfunction. Not only will things go away,
EPRO program contents can be easily changed by key input etc.
There is no need to rewrite to M, increasing efficiency.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing a portion of a memory device according to an embodiment of the present invention. 1...Inverter, 2...2 input AN
D gate, 3…. ...Decoder, 4...RAM
Memory chip, a...Inverter input status, b
...Inverter output terminal, c...2 input AND
Gate input terminal, d...2 input AND gate input terminal, e...Decoder control status, i, g...
Upper bit address input terminal, h...Decoder chip select output terminal, i...RAM memory chip select terminal, j...RAM memory address input terminal, k... ...RAM memory data input terminal, 1...RAM/memory write control terminal, m...2 input AND gate output terminal, S
．． ...Read signal, S2... Weighting signal, AB... Address signal, AB'... Upper bit address signal, DB... Data bus, R...
Resistor, SW...Switch.

Claims (1)

[Claims] 1. A memory chip, a signal line for supplying addresses and data to the memory chip, a decoder that generates a chip select signal for selecting a memory chip based on chip select data, and a chip select signal from the decoder for supplying the chip select signal to the memory chip. As a result, a chip select signal supply line for activating the memory chip, a signal line for supplying a write control signal for writing data to the memory chip, and a signal line for supplying a write control signal for writing data to the memory chip, and a signal line for supplying the write inhibit signal to the memory chip in response to the write inhibit signal and read control signal. a gate circuit that inactivates the decoder during a period in which the read control signal is generated and generates a signal that activates the decoder during the period in which the write inhibit signal is generated and the read control signal is generated; A memory device comprising: