JPS62138258U - - Google Patents
Info
- Publication number
- JPS62138258U JPS62138258U JP1986025690U JP2569086U JPS62138258U JP S62138258 U JPS62138258 U JP S62138258U JP 1986025690 U JP1986025690 U JP 1986025690U JP 2569086 U JP2569086 U JP 2569086U JP S62138258 U JPS62138258 U JP S62138258U
- Authority
- JP
- Japan
- Prior art keywords
- memory
- command signal
- write
- cpu
- write command
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
Landscapes
- Storage Device Security (AREA)
Description
図は本考案の一実施例を示す回路図である。
１……ＥＥＰＲＯＭ、２……ゲート回路、３…
…ＣＰＵ、５……設定用スイツチ。
The figure is a circuit diagram showing an embodiment of the present invention. 1... EEPROM, 2... Gate circuit, 3...
...CPU, 5...Setting switch.
Claims (1)
力されている間は書き込み可能状態となるメモリ
と、前記メモリに対して書き込み指令信号を供給
しつつデータ設定動作を行うＣＰＵと、前記ＣＰ
Ｕが書き込み指令信号を出力すべきか否かを択一
的に指示するスイツチとを備えたメモリの書き込
み制御回路において、前記スイツチが前記ＣＰＵ
に対して書き込み指令信号を出力すべきでない旨
の指令を出力しているときには前記ＣＰＵから前
記メモリに供給される書き込み指令信号を阻止し
、書き込み指令信号を出力するべきである旨の指
令を出力しているときには前記ＣＰＵから前記メ
モリに供給される書き込み指令信号を許容するゲ
ート手段を備えたメモリの書き込み制御回路。 a memory that is enabled for writing while a write command signal is input to a write enable terminal; a CPU that performs a data setting operation while supplying a write command signal to the memory;
In the memory write control circuit, the memory write control circuit includes a switch that selectively instructs whether or not U should output a write command signal, the switch
When outputting a command to the effect that a write command signal should not be output to the CPU, the write command signal supplied from the CPU to the memory is blocked, and a command to the effect that the write command signal should be output is output. A write control circuit for a memory, comprising gate means for allowing a write command signal supplied from the CPU to the memory when the CPU is running.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986025690U JPS62138258U (en) | 1986-02-26 | 1986-02-26 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986025690U JPS62138258U (en) | 1986-02-26 | 1986-02-26 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS62138258U true JPS62138258U (en) | 1987-08-31 |
Family
ID=30826081
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986025690U Pending JPS62138258U (en) | 1986-02-26 | 1986-02-26 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS62138258U (en) |
Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS586568A (en) * | 1982-06-22 | 1983-01-14 | Nec Corp | Memory device |
| JPS5880200A (en) * | 1981-11-04 | 1983-05-14 | Mitsubishi Electric Corp | Memory protecting circuit |
-
1986
- 1986-02-26 JP JP1986025690U patent/JPS62138258U/ja active Pending
Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5880200A (en) * | 1981-11-04 | 1983-05-14 | Mitsubishi Electric Corp | Memory protecting circuit |
| JPS586568A (en) * | 1982-06-22 | 1983-01-14 | Nec Corp | Memory device |
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