JPS6076430U - Memory battery power supply - Google Patents
Memory battery power supplyInfo
- Publication number
- JPS6076430U JPS6076430U JP16610183U JP16610183U JPS6076430U JP S6076430 U JPS6076430 U JP S6076430U JP 16610183 U JP16610183 U JP 16610183U JP 16610183 U JP16610183 U JP 16610183U JP S6076430 U JPS6076430 U JP S6076430U
- Authority
- JP
- Japan
- Prior art keywords
- power supply
- memory
- battery
- circuit
- battery power
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のメモリ電池電源装置の一例を示すブロッ
ク図、傘２図はこの考案の一実施例を示すブロック図で
ある。
１１・・・電池、１２・・・時計回路、１３・・・制御
回路、１４・・・メモリ回路、１５・・・入出力回路、
１６・・・昇圧回路。FIG. 1 is a block diagram showing an example of a conventional memory battery power supply device, and FIG. 2 is a block diagram showing an embodiment of this invention. 11... Battery, 12... Clock circuit, 13... Control circuit, 14... Memory circuit, 15... Input/output circuit,
16... Booster circuit.
Claims (1)
・読出時に必要な電源電圧の下限値より低いメモリ回路
と、このメモリ回路の動作を制御する制御回路と、前記
メモリ回路及び制御回路に所定の電源電圧を供給する電
池とを有してなるメモリ用電池電源装置において、前記
制御回路からの制御指令信号に応答して前記電池の電圧
を昇圧する昇圧回路を設け、データ保持時には前記電池
からの電圧を、データ書込・読取時には前記昇圧回路か
らの電圧を前記メモリ回路及び制御回路に供給する事を
特徴とするメモリ用電池電源装置。a memory circuit whose lower limit of power supply voltage required for data retention is lower than the lower limit of power supply voltage required for data writing/reading; a control circuit for controlling the operation of this memory circuit; In a memory battery power supply device comprising a battery that supplies a predetermined power supply voltage, a booster circuit is provided that boosts the voltage of the battery in response to a control command signal from the control circuit, and when data is retained, the battery A battery power supply device for a memory, characterized in that the voltage from the booster circuit is supplied to the memory circuit and the control circuit during data writing/reading.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16610183U JPS6076430U (en) | 1983-10-28 | 1983-10-28 | Memory battery power supply |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16610183U JPS6076430U (en) | 1983-10-28 | 1983-10-28 | Memory battery power supply |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6076430U true JPS6076430U (en) | 1985-05-28 |
Family
ID=30363726
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16610183U Pending JPS6076430U (en) | 1983-10-28 | 1983-10-28 | Memory battery power supply |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6076430U (en) |
-
1983
- 1983-10-28 JP JP16610183U patent/JPS6076430U/en active Pending
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