JPS586568A - Memory device - Google Patents

Abstract

PURPOSE:To avoid data from being written in an RAM chip except specified write, by providing a control circuit which makes the RAM chip of a memory board non-selective and a non-selection signal to the RAM chip. CONSTITUTION:An AND gate 2 is connected to an RAM chip 4 on a memory board via a decoder 3 and an output of an inverter 1 and a data readout signal S1 are given to the input of gate 2. A voltage of +5V is applied to the input of an inverter 1 via a resistor R and grounded via a switch (SW). When the SW is at OFF state, the decoder 3 is made active independently of the state of a signal S1, and the decoder 3 inputs a chip selection signal designed with an upper-order bit address signal AB' to the RAM 4, the address information outputted from a CPU is inputted via a bus AB and a data is inputted via a bus DB is response to a write signal S2. With the SW at ON state, the decoder 3 is made inhibited and the RAM4 is inhibited either.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is based on the mechanical cutting device m4? The present invention relates to a memory device including a readable/writable memory element.

Conventional readable and writable memory (hereinafter referred to as 8M)
The RAM element mounted on the board is used as a program storage area during program development, program commands are written in this RAM, and then when the program is executed, the predetermined processing procedure and the like are executed. , #! The central processing unit (CPU) may execute the above nine processing steps. This is mainly due to the addition of a write signal due to preprogramming in the noise, but also due to the addition of write signals due to noise or program instructions. There is a drawback that even the regular program data written in the RAMK used as a program storage area is rewritten.

SUMMARY OF THE INVENTION An object of the present invention is to provide a RAM device in which a program instruction written in a RAM element is not easily rewritten into program information due to a program error in noise.

The present invention provides a control circuit that unselects a RAM chip on a memory board, and provides a non-selection signal to the RAM chip from this control circuit. It is configured to be written and read.

According to the present invention, writing of data to the RAM is prohibited by the non-selection signal from the IIcFi control circuit except for a predetermined period, so that a regular program written in kRAMK for a predetermined period is not affected by noise or programming. Information will not be rewritten to incorrect information by mistakes.

The present invention will be explained in detail below with reference to one drawing.

FIG. 1 is a block diagram showing a part of a memory device showing one embodiment of the present invention. The RAM chip 4 on the memory board has an input/output terminal k of a data bus DS and an input terminal j of an address bus AB, and a write signal 8. is input, and a chip select signal is input from the chip select terminal of the decoder 3 to the terminal l. On the other hand, decoder 3
The upper bit of the address signal for preselect is B.
' (in this embodiment, the upper two bits) is input to the terminal f9g. A decoder control signal is inputted to the terminal e from the output terminal m of the i; The input terminal 1 of the inverter 1 is connected to the input terminal 1 of the inverter 1, to which a voltage of +5V is applied via the resistor B and is grounded via the switch SW.

According to this embodiment having such a configuration, when the switch SW is OFF
In this state, the input terminal a of the inverter is connected to +5 through the resistor R.
Since it is pulled up to V, the Ill level is input, the IQ level is output from the output terminal of the inverter 1, and this signal enters one input terminal C of the two-man power AND gate 2.

That is, the signal IQ is output to the output terminal m of the two-man power AND gate 2, and this signal enters the chip select terminal e of the decoder 3, so that the decoder 3 becomes active. On the other hand, the input terminal C of the two-man-powered AND gate 20 is connected to the switch SW.
Since it is at the ft@Qm level as long as it is OFF, the terminal mlc is always 0 regardless of whether the data read signal Ss at the other input terminal d of the two-man AND gate 2 is IQI or 11-. - level is output, so the decoder 3 is in the active state. Decoder 3 in active state
The upper bit address signal B' is inputted to each input terminal f1g of the decoder 3, and depending on the combination of the levels of the input signals, the upper bit address signal B' specified by the upper bit address signal B' of the plurality of output terminals of the decoder 3 is inputted. The e6s level is input from the chip select signal output terminals to the chip select terminal j of 8λM4, and the 8λM chip 4 becomes active JllK.

The address information output from the CPU is input to the RAM address λ power terminal jK through the address information module B, and the data write signal is input to the input/output control terminal 1 of the RAM address module M4 at a level II of 8 degrees (in this example, 1o@ level), data is input to the data input terminal h of the memory M4 via the data bus DB.

On the other hand, when the switch 8W is in the ON state MK, the input terminal a of the inverter l becomes the #o@ level, so the inverter output terminal tl'' becomes the l- level and enters the input terminal C of the two-manufactured AND gate 20.At this time, the AND gate 20 input terminal dic
Data read signal 8. is input, (the read signal is @Oa only when the CPU reads the contents of RAM4.
Level K fk') b 11- for other operations
Suppose that it is a level signal. )AND gate output terminal m
is set to 10 levels only when the CPU reads the inside of the memory, and at other times, a signal of level 11 is output and input to the chip select terminal e of the decoder 3. When the chip select terminal is 61 levels, that is, except during the data read period, the decoder 3 is in the disabled state, and 11 levels are input from the decoder output terminal to the RAM 4 chip select terminal lK, and the RAM memory 4 is in the disabled state. Become. In addition, when the read signal uO level is input to the terminal d, 10 lbel is output to the chip select terminal e of the decoder 3, the decoder 3 becomes active, and the upper bit of the address signal is output from the decoder output terminal. The level signal specified by λB' should be selected.
0-t'R is output to AM chip 4 and sent to chip select terminal i t-10°m'be/' of RAM memory 4.
AM4 is not in the active state, and the data stored at the address specified by the address signal AB is read out through the data bus DB. RAM40 input control terminal 1 has CPU
The IQ level is output only when reading data into RAM4, and during other operations.

Ill level signal 8t is input. This signal is Iol
However, when the chip select terminals of R and AM4 are at 11 lbs, that is, when the switch is in the ON state and the read signal S□ is 11 lbs.

Since the RAM chip 4 becomes a prohibition letter 11, writing of data is prohibited. Therefore, at this time, the RAM chip 4 becomes read-only.

As described above, if this embodiment of IIC% is implemented, data can be written to RAM chip 4 by turning off the switch SW.

When the switch is turned on, RAM is
Chip 4 operates as a read-only memory. For the sake of humanity, the noise and noise that arises in the program depack trend
Writing of data to the %RAM RAM chip by a device or the like can be prevented by keeping the switch OFF.

In this embodiment, a manual switch is used as the switch, but it may also be a front gate so that it is turned off only when data is being written under program control. Also, in this embodiment, the chip select signal of the decoder is controlled! Although the RAM chip is disabled, it is also possible to directly add a signal to deselect the RAM chip without using a decoder.

In addition, as an application of the present invention, if the RAM chip and control circuit of the present invention are used as a storage area for programs and data during program development in a microcomputer system, the RAM chip and control circuit of the present invention can be used as a storage area for programs and data during program development. Not only will the current program be destroyed and no stone fist will appear, but the contents of the program can be easily changed with key human power, etc., and the efficiency of rewriting to HFROM will be improved.

[Brief explanation of the drawing]

FIG. 1 is a schematic diagram showing a portion of a memory device according to an embodiment of the present invention.

Claims (1)

[Claims] A memory device that sends and receives information under control of a read signal and a write signal, characterized by having means for generating a control signal so as not to accept the write signal during the period during which the control signal is generated. memory device.