JPS60126846U - Memory switching control circuit - Google Patents
Memory switching control circuitInfo
- Publication number
- JPS60126846U JPS60126846U JP1147284U JP1147284U JPS60126846U JP S60126846 U JPS60126846 U JP S60126846U JP 1147284 U JP1147284 U JP 1147284U JP 1147284 U JP1147284 U JP 1147284U JP S60126846 U JPS60126846 U JP S60126846U
- Authority
- JP
- Japan
- Prior art keywords
- memory
- memory switching
- control circuit
- switching control
- microprocessor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
第１図は従来のデータ作成装置の構成例を示すブロック
図、第２図は第１図におけるメモリ切換え回路の構成例
を示すブロック図、第３図は本考案が採用されるデータ
作成装置の構成例を示すブロック図、第４図は第３図に
おけるメモリ切換回路の実施例を示すブロック図、第５
図は本考案にて使用されるＲＯＭのメモリマツプを示す
図である。
３８・・・マイクロプロセッサ、４０・・・メモリ切換
え回路、４１・・・ＲＯＭ、４０１・・・ページ切換え
レジスタ、４０２・・・アドレスデコーダ。FIG. 1 is a block diagram showing a configuration example of a conventional data creation device, FIG. 2 is a block diagram showing a configuration example of the memory switching circuit in FIG. 1, and FIG. 3 is a block diagram showing a configuration example of a conventional data creation device. 4 is a block diagram showing an example of the configuration; FIG. 4 is a block diagram showing an embodiment of the memory switching circuit in FIG. 3; FIG.
The figure shows a memory map of the ROM used in the present invention. 38... Microprocessor, 40... Memory switching circuit, 41... ROM, 401... Page switching register, 402... Address decoder.
Claims (1)
グラムにより装置制御を行なうデータ作成装置において
、同一アドレス空間に割付けられた異種プログラムが格
納されるメモリと、電源、 ＯＮ時に生成されるイニシ
ャルリセット信号によ−りリセットされ、上記マイクロ
プロセッサから発せられるメモリ切換え指示に基づき任
意の値が設定されるレジスタと、このレジスタに設定さ
れた値を上記メモリへ供給すべきアドレスの最上位ビッ
トとして付加し、このビットの内容に従かつそメモリ切
換えを行ない上記いずれか一方のプログラムを有効にす
ることを特徴とするメモリ切換え制御回路。 ・
゛In a data creation device that uses a microprocessor as its core and controls the device using a program stored in memory, there is a memory that stores different programs allocated to the same address space, and an initial reset signal that is generated when the power is turned on. - a register that is reset and set to an arbitrary value based on a memory switching instruction issued from the microprocessor; the value set in this register is added as the most significant bit of the address to be supplied to the memory; A memory switching control circuit characterized in that it performs memory switching according to the contents of bits to enable one of the above programs.・
゛
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1147284U JPS60126846U (en) | 1984-01-30 | 1984-01-30 | Memory switching control circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1147284U JPS60126846U (en) | 1984-01-30 | 1984-01-30 | Memory switching control circuit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60126846U true JPS60126846U (en) | 1985-08-26 |
Family
ID=30493623
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1147284U Pending JPS60126846U (en) | 1984-01-30 | 1984-01-30 | Memory switching control circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60126846U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63106026A (en) * | 1986-10-23 | 1988-05-11 | Sanyo Electric Co Ltd | Information processor |
-
1984
- 1984-01-30 JP JP1147284U patent/JPS60126846U/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS63106026A (en) * | 1986-10-23 | 1988-05-11 | Sanyo Electric Co Ltd | Information processor |
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