JPS5942599U - semiconductor integrated circuit - Google Patents

semiconductor integrated circuit

Info

Publication number
JPS5942599U
JPS5942599U JP13670882U JP13670882U JPS5942599U JP S5942599 U JPS5942599 U JP S5942599U JP 13670882 U JP13670882 U JP 13670882U JP 13670882 U JP13670882 U JP 13670882U JP S5942599 U JPS5942599 U JP S5942599U
Authority
JP
Japan
Prior art keywords
integrated circuit
semiconductor integrated
read
memory
addressed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP13670882U
Other languages
Japanese (ja)
Inventor
佐瀬　柳一
Original Assignee
日本電気株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 日本電気株式会社 filed Critical 日本電気株式会社
Priority to JP13670882U priority Critical patent/JPS5942599U/en
Publication of JPS5942599U publication Critical patent/JPS5942599U/en
Pending legal-status Critical Current

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Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は、本考案による１実施例を示す図である。 １・・・ＦＲＯＭ書き換え制御回路、２・・・アドレス
デコーダー、３・・・アドレスデコーダー、４・・・マ
スクＲＯＭ部、５・・・ＰＲＯＭ部、６・・・マスクＲ
ＯＭセル、７・・・ＦＲＯＭセル、８・・・１ビツト出
力線、９・・・アドレスデコーダ２の出力線、１０・・
・アドレスデコーダ３の出力線、１１・・・トランスフ
ァーゲート。FIG. 1 is a diagram showing one embodiment of the present invention. DESCRIPTION OF SYMBOLS 1...FROM rewrite control circuit, 2...Address decoder, 3...Address decoder, 4...Mask ROM section, 5...PROM section, 6...Mask R
OM cell, 7...FROM cell, 8...1 bit output line, 9...Output line of address decoder 2, 10...
- Output line of address decoder 3, 11...transfer gate.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 読出し専用メモリーと書き換え可能な読出し専用メモリ
ーとを内蔵し該２種類の読出し専用メモリーを同一のア
ドレス手段によりアドレスしうるようにしたことを特徴
とする半導体集積回路。A semiconductor integrated circuit comprising a built-in read-only memory and a rewritable read-only memory, and the two types of read-only memories can be addressed by the same addressing means.
JP13670882U 1982-09-09 1982-09-09 semiconductor integrated circuit Pending JPS5942599U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP13670882U JPS5942599U (en) 1982-09-09 1982-09-09 semiconductor integrated circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP13670882U JPS5942599U (en) 1982-09-09 1982-09-09 semiconductor integrated circuit

Publications (1)

Publication Number Publication Date
JPS5942599U true JPS5942599U (en) 1984-03-19

Family

ID=30307292

Family Applications (1)

Application Number Title Priority Date Filing Date
JP13670882U Pending JPS5942599U (en) 1982-09-09 1982-09-09 semiconductor integrated circuit

Country Status (1)

Country Link
JP (1) JPS5942599U (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008091005A (en) * 2006-09-05 2008-04-17 Semiconductor Energy Lab Co Ltd Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2008091005A (en) * 2006-09-05 2008-04-17 Semiconductor Energy Lab Co Ltd Semiconductor device

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