JPS6284842U - - Google Patents
Info
- Publication number
- JPS6284842U JPS6284842U JP17614085U JP17614085U JPS6284842U JP S6284842 U JPS6284842 U JP S6284842U JP 17614085 U JP17614085 U JP 17614085U JP 17614085 U JP17614085 U JP 17614085U JP S6284842 U JPS6284842 U JP S6284842U
- Authority
- JP
- Japan
- Prior art keywords
- memory
- pal
- array logic
- programmable array
- memory device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 230000006870 function Effects 0.000 claims 2
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Static Random-Access Memory (AREA)
- Storage Device Security (AREA)
Description
第１図は従来例を説明するためのブロツク線図
、第２図は本考案の一実施例を説明するためのブ
ロツク線図である。
（符号の説明）、１……アドレスコーダ、２…
…ＡＮＤ素子、３……メモリ、１１……プログラ
マブルアレイロジツクス（ＰＡＬ）、１２……ゲ
ート回路、１３……メモリ、１４……ゲート回路
。
FIG. 1 is a block diagram for explaining a conventional example, and FIG. 2 is a block diagram for explaining an embodiment of the present invention. (Explanation of codes), 1...address coder, 2...
...AND element, 3...memory, 11...programmable array logic (PAL), 12...gate circuit, 13...memory, 14...gate circuit.
Claims (1)
）を同一メモリチツプの中に組入れてメモリのチ
ツプセレクト信号の制御に用い、上記プログラマ
ブルアレイロジツクス（ＰＡＬ）に書込むプログ
ラム内容をアドレスラインもしくはデータライン
から供給するよう構成したことを特徴とするアド
レスデコード機能付メモリ装置。 (2) 実用新案登録請求の範囲第１項において、
前記メモリ装置が消去可能なプログラム可能読取
専用メモリ（ＥＰＲＯＭ）である場合と電気的に
消去可能なプログラム可能読取専用メモリ（ＥＥ
ＰＲＯＭ）である場合に上記プログラマブルアレ
イロジツクス（ＰＡＬ）を同一方式のロジツクス
で構成できるようにしたことを特徴とするアドレ
スデコード機能付メモリ装置。[Scope of utility model registration claims] (1) Programmable array logic (PAL)
) is incorporated into the same memory chip and used to control the chip select signal of the memory, and the program content to be written to the programmable array logic (PAL) is supplied from the address line or the data line. Memory device with decoding function. (2) In paragraph 1 of the claims for utility model registration,
The memory device may be an erasable programmable read only memory (EPROM) or an electrically erasable programmable read only memory (EE).
1. A memory device with an address decoding function, characterized in that when the programmable array logic (PAL) is a PROM), the programmable array logic (PAL) can be configured with logic of the same type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17614085U JPS6284842U (en) | 1985-11-18 | 1985-11-18 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP17614085U JPS6284842U (en) | 1985-11-18 | 1985-11-18 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6284842U true JPS6284842U (en) | 1987-05-30 |
Family
ID=31116102
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP17614085U Pending JPS6284842U (en) | 1985-11-18 | 1985-11-18 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6284842U (en) |
-
1985
- 1985-11-18 JP JP17614085U patent/JPS6284842U/ja active Pending
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