JPH0330149U - - Google Patents
Info
- Publication number
- JPH0330149U JPH0330149U JP8811989U JP8811989U JPH0330149U JP H0330149 U JPH0330149 U JP H0330149U JP 8811989 U JP8811989 U JP 8811989U JP 8811989 U JP8811989 U JP 8811989U JP H0330149 U JPH0330149 U JP H0330149U
- Authority
- JP
- Japan
- Prior art keywords
- rom
- ram
- decode signal
- output
- selection signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 1
Description
第１図はこの考案のメモリ領域切り換え制御回
路の一実施例を示すブロツク図、第２図〜第４図
は同実施例におけるメモリマツプ、第５図は従来
例におけるメモリマツプである。
６…アドレスデコーダ、７…Ｉ／Ｏインターフ
エース、８Ａ，８Ｂ…ＡＮＤゲート、９…インバ
ータ、Ａ…デコード信号、Ｂ…出力ポート信号（
選択信号）、ＣＳ１，ＣＳ２…チツプセレクト信
号。
FIG. 1 is a block diagram showing one embodiment of the memory area switching control circuit of this invention, FIGS. 2 to 4 are memory maps of the same embodiment, and FIG. 5 is a memory map of a conventional example. 6... Address decoder, 7... I/O interface, 8A, 8B... AND gate, 9... Inverter, A... Decode signal, B... Output port signal (
selection signal), CS1, CS2...chip select signal.
Claims (1)
およびＲＡＭに出力するアドレスデコーダと、 ＲＯＭまたはＲＡＭに対応して選択信号を出力
するＩ／Ｏインターフエースと、 選択信号がＲＯＭを選択することを示すときに
ＲＯＭに出力されるデコード信号を有効にすると
ともにＲＡＭに出力されるデコード信号を無効に
し、選択信号がＲＡＭを選択することを示すとき
にＲＯＭに出力されるデコード信号を無効にする
とともにＲＡＭに出力されるデコード信号を有効
にする組み合わせ回路とを有することを特徴とす
るメモリ領域切り換え制御回路。[Scope of claim for utility model registration] Decoded signals according to address data in ROM
and an address decoder that outputs to RAM, an I/O interface that outputs a selection signal corresponding to ROM or RAM, and a decode signal that enables the decode signal that is output to ROM when the selection signal indicates that ROM is selected. A combinational circuit that simultaneously disables the decode signal output to the RAM, and disables the decode signal output to the ROM and enables the decode signal output to the RAM when the selection signal indicates that the RAM is selected. A memory area switching control circuit comprising:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8811989U JPH0330149U (en) | 1989-07-28 | 1989-07-28 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP8811989U JPH0330149U (en) | 1989-07-28 | 1989-07-28 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0330149U true JPH0330149U (en) | 1991-03-25 |
Family
ID=31637752
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP8811989U Pending JPH0330149U (en) | 1989-07-28 | 1989-07-28 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0330149U (en) |
-
1989
- 1989-07-28 JP JP8811989U patent/JPH0330149U/ja active Pending
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