JPS6425235U - - Google Patents
Info
- Publication number
- JPS6425235U JPS6425235U JP11942287U JP11942287U JPS6425235U JP S6425235 U JPS6425235 U JP S6425235U JP 11942287 U JP11942287 U JP 11942287U JP 11942287 U JP11942287 U JP 11942287U JP S6425235 U JPS6425235 U JP S6425235U
- Authority
- JP
- Japan
- Prior art keywords
- pull
- output circuit
- switching control
- control signal
- mos transistor
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Logic Circuits (AREA)
- Microcomputers (AREA)
Description
第１図は本考案の実施例を示す回路図、第２図
は従来例を示す回路図である。
６……第１ＭＯＳトランジスタ、７……第２Ｍ
ＯＳトランジスタ、８……出力端子、９……ＮＡ
ＮＤゲート、１０，１２……ＮＯＲゲート、１３
……ラツチ回路、１４……ＥＰ―ＲＯＭ。
FIG. 1 is a circuit diagram showing an embodiment of the present invention, and FIG. 2 is a circuit diagram showing a conventional example. 6...First MOS transistor, 7...Second M
OS transistor, 8...output terminal, 9...NA
ND gate, 10, 12...NOR gate, 13
...Latch circuit, 14...EP-ROM.
Claims (1)
用の第１ＭＯＳトランジスタと、前記出力端子に
ドレインが接続されたプルアツプあるいはプルダ
ウン用の第２ＭＯＳトランジスタと、該第２ＭＯ
Ｓトランジスタのゲートにデータ信号を印加する
か遮断するかを制御する切換制御信号が印加され
たゲート回路と、前記切換制御信号を発生するた
めの情報が記憶された領域を有する不揮発性メモ
リ（ＥＰ―ＲＯＭ）とを備え、前記不揮発性メモ
リの前記領域に記憶された情報に基いて、オープ
ンドレイン形式の出力回路とプルアツプあるいは
プルダウン形式の出力回路とを選択可能としたプ
ログラマブル出力回路。 a first MOS transistor for an output driver whose drain is connected to the output terminal; a second MOS transistor for pull-up or pull-down whose drain is connected to the output terminal;
A non-volatile memory (EP) has a gate circuit to which a switching control signal is applied that controls whether to apply or cut off a data signal to the gate of the S transistor, and an area in which information for generating the switching control signal is stored. - A programmable output circuit, comprising: a ROM), and is capable of selecting an open-drain type output circuit and a pull-up or pull-down type output circuit based on information stored in the area of the nonvolatile memory.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11942287U JPS6425235U (en) | 1987-08-04 | 1987-08-04 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP11942287U JPS6425235U (en) | 1987-08-04 | 1987-08-04 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS6425235U true JPS6425235U (en) | 1989-02-13 |
Family
ID=31364638
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP11942287U Pending JPS6425235U (en) | 1987-08-04 | 1987-08-04 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6425235U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0590950A (en) * | 1991-03-29 | 1993-04-09 | Kawasaki Steel Corp | Semiconductor integrated circuit |
-
1987
- 1987-08-04 JP JP11942287U patent/JPS6425235U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0590950A (en) * | 1991-03-29 | 1993-04-09 | Kawasaki Steel Corp | Semiconductor integrated circuit |
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