JPS63157899U - - Google Patents
Info
- Publication number
- JPS63157899U JPS63157899U JP4839087U JP4839087U JPS63157899U JP S63157899 U JPS63157899 U JP S63157899U JP 4839087 U JP4839087 U JP 4839087U JP 4839087 U JP4839087 U JP 4839087U JP S63157899 U JPS63157899 U JP S63157899U
- Authority
- JP
- Japan
- Prior art keywords
- input terminal
- address signal
- address
- latch
- decoder
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Description
第１図はこの考案の一実施例のブロツク図、第
２図は従来例のブロツク図である。
１……ＲＯＭ（本考案）、２……メモリセルア
レイ、３……デコーダ、４……アドレスラツチ回
路、５……データ出力端子群、６……アドレス入
力端子群、７……制御入力端子群、８……ラツチ
入力端子、９……ＲＯＭ（従来例）、１０……ラ
ツチＩＣ。
FIG. 1 is a block diagram of one embodiment of this invention, and FIG. 2 is a block diagram of a conventional example. 1...ROM (this invention), 2...Memory cell array, 3...Decoder, 4...Address latch circuit, 5...Data output terminal group, 6...Address input terminal group, 7...Control input terminal group , 8... Latch input terminal, 9... ROM (conventional example), 10... Latch IC.
Claims (1)
するデコーダと、アドレス信号をラツチするラツ
チ回路とを内蔵し、データ出力端子と、アドレス
入力端子と、制御入力端子と、ラツチ入力端子と
を備える半導体メモリ装置。 A semiconductor memory device incorporating a memory cell array, a decoder for decoding an address signal, and a latch circuit for latching an address signal, and comprising a data output terminal, an address input terminal, a control input terminal, and a latch input terminal.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4839087U JPS63157899U (en) | 1987-03-31 | 1987-03-31 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4839087U JPS63157899U (en) | 1987-03-31 | 1987-03-31 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS63157899U true JPS63157899U (en) | 1988-10-17 |
Family
ID=30869873
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4839087U Pending JPS63157899U (en) | 1987-03-31 | 1987-03-31 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63157899U (en) |
Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60113396A (en) * | 1983-11-25 | 1985-06-19 | Toshiba Corp | Memory lsi |
| JPS61134998A (en) * | 1984-12-04 | 1986-06-23 | Nec Corp | Read-only memory |
| JPS61187197A (en) * | 1985-02-14 | 1986-08-20 | Nec Corp | Read only memory |
-
1987
- 1987-03-31 JP JP4839087U patent/JPS63157899U/ja active Pending
Patent Citations (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS60113396A (en) * | 1983-11-25 | 1985-06-19 | Toshiba Corp | Memory lsi |
| JPS61134998A (en) * | 1984-12-04 | 1986-06-23 | Nec Corp | Read-only memory |
| JPS61187197A (en) * | 1985-02-14 | 1986-08-20 | Nec Corp | Read only memory |
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