JPS61187197A - Read only memory - Google Patents

Abstract

PURPOSE:To decrease the read time by latching an address of a storage data to be read next during the read period of the storage data of an address latched to any of the 1st and 2nd address latches to other address latch. CONSTITUTION:When the 2nd chip enable input (f) reaches a low level, and after the signal (g) goes to a low level, the counter in the 1st control circuit 52 counts several pulses, a gate signal (l) is outputted from the 1st control circuit 52 to a memory data latch 64, then the 2nd control circuit 62 receives a signal from the circuit 52 to send a signal (k) to a multiplexer 63 to select the data of the 1st address latch 54. Then a ROM53 is brought into the pre- charge state or sampling state according to the input (f), and after several pulses are counted when the ROM53 is sampled, the latch 64 receives the signal (l) to switch the input destination of the multiplexer 63 and every time a next address write signal (h) is inputted, gate signals (i, j) are sent alternately to the 1st and 2nd latches 54, 55.

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to a low-speed operation read-only memory (hereinafter referred to as ROM).
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[Conventional technology]

When reading data stored in a ROM, a waiting time is required from address setting to obtaining data output. In ordinary OMs with high-speed operation, this waiting time is shorter than the machine cycle time of the central processing unit (hereinafter referred to as CPU).
ROM that does not require extra time but operates at low speed
ICs may require waiting time that exceeds the machine cycle time of the CPU.

A conventional example is shown below using the figure. 8g3 and 4 are block diagrams and timing diagrams of an example of a conventional dynamic ROM. The control circuit 2 is.

In response to the change of the input a from the chip enable input terminal 1 from low level to high level, the signal S sent to the ROM section 3 is set to high level to put the inside of the 80M section 3 into a precharge state.

Next, in response to the chip enable signal a changing to low level, the control circuit 2 outputs the gate signal C to the address latch 4 to latch the address data input from the address input terminals 5 to 8. After the counter in the control circuit 2 counts several times as the chip enable input a changes to low level, the control circuit 2 sets the signal S to low level and uses it as a read signal for the 80M section 3.
The inside of the 0M unit 3 shifts to a sampling state in which storage data selected by the address data latched in the address data latch 4 is output.

After several tens of counts after the signal S becomes low level, the control circuit 2 outputs the gate signal d to the storage data latch 9, and the storage data latch 9 latches the storage data output from the 80M section 3. Memory data output terminal 1
Outputs stored data to 0-13. The control circuit 2 simultaneously outputs a ready signal e indicating that data has been output to the 14 ready signal output terminals. The CPU confirms this ready signal e and retrieves the stored data.

(Problems to be Solved by the Invention) In the conventional ROM described above, it takes several machine cycles from setting the address to outputting the ready signal.
U has a drawback that the 80M section cannot be accessed again during the machine cycle until the ready signal is output.

The present invention eliminates the above drawbacks and provides two address latches: an address latch for stored data to be read, and an address latch capable of holding the address of stored data to be read next during a machine cycle during the waiting time for outputting stored data. The present invention provides a ROM that has a systematic address latch, effectively uses the waiting time until output of a ready signal, and can shorten the read time.

Means for Solving Problem C) The read-only memory of the present invention includes first and second address latches, and stores data at an address latched in either of the first or second address latches. The present invention is characterized in that the address of the storage data to be read next during the read period is latched in addition to the first and second address latches.

(Example) Hereinafter, the present invention will be explained by examples with reference to the drawings.

1 and 2 are block diagrams and timing diagrams of one embodiment of the present invention, in which the first control circuit 52 receives an input f from the chip enable input terminal 51 changing from low level to high level. The signal g sent to the section 53 is set to high level to put the inside of the ROM section 53 in a precharged state.

Next, in response to the chip enable input f changing to low level, the first control circuit 52 to the second control circuit 62
send a signal to. The second control circuit 62 is the first control circuit 5
Upon receiving the signal from the address data input terminals 57 to 60, the first address latch 54 first sends a gate signal i to the first address latch 54, and the first address latch 54, which receives the gate signal i, latches the input address data from the address data input terminals 57 to 60. . The multiplexer 63 selects the data in the first address latch 54 in response to a signal k from the first control circuit 62.

After counting, the first control circuit 52 sets the signal g to a low level as a read signal, and shifts to a sampling state in which nine stored data selected by the address data output from the 80M unit 53t-multiplexer 63 are output. When a next address write signal is input from the input terminal 61 during this sampling state, the second control circuit 62 receives it and outputs a gate signal j to the second address latch 55, and the second address latch 55 receives it. In response, the address data input terminals 57 to 60 latch the input address data. At this time, a signal NA indicating that the next address has been latched is output from the second control circuit 62 to the first control circuit 52.

Since the signal Bt from the first control circuit 52 to the 80M section 53 turns to low level, the counter in the I-th control circuit 52 counts several tens of times, and then the first control circuit 52
The input signal e is output to the storage data latch 64,
The storage data latch 64 receives it, latches the storage data, and outputs the storage data to the storage data output terminals 65 to 68. At the same time, the first control circuit 52 outputs a ready signal m indicating that the stored data has been output to the ready signal output terminal 69.

Next time the ROM is accessed, that is, when the input f of the chip enable input terminal 51 becomes high level, the second control circuit 62, which remembers that the netast address has been latched, responds to this by switching the multiplexer. A signal k for switching the input of 63 to the second address latch 55 is output to the multiplexer 63. When the input f returns to low level, the 8g2 control circuit 62, which remembers that the next address has been latched, does not output the gate signal for address data latch, and the second control circuit 62 receives the signal NAt-. The first control circuit 52 sets the signal g to the 80M section 53 to low level as a read signal, and
The 80M unit 53 is shifted to a sampling state. At this time, the address is determined by the data latched in the second address latch 55. Also, when a next address write signal is input from the input terminal 61 during this sampling state, the second control circuit 62 sends a gate signal i to the first address latch 54 that is not contributing to address data at this time. The address data is latched in the first address latch 5417C.

In addition, the second chip enable input signal f does not go to low level, and after the signal g goes to low level, the first control circuit 5
After the kakunta in 2 counts several tens, the gate signal e is output from the first control circuit 52 to the storage data latch 64, and then the second control circuit 62 outputs the gate signal e to the storage data latch 64.
The receiver receives a signal from the address latch 54 and sends a signal k to the seventh multiplexer 63 to select the data in the first address latch 54.

Thereafter, in the same way as the above operation, the chip enable manual flc
Therefore, the 80M unit 53 is set to the precharge state M or the sampling state, and after a certain period of several tens of counts after the 80M unit 53 is set to the sampling state, the storage data latch 64 is opened.
The cutting edge of the multiplexer 630 is switched after receiving the gate signal l, and each time the next address write signal is input, the first and second address latches 54.5
Gate signals i and j are alternately sent to the terminals 5 and 5.

(Effects of the Invention) As explained in detail above, the OM of the present invention writes the address of the next data to be read during the waiting time until the data is output.
Since there is no need to take the time to write an address, there is a tremendous effect that the read time can be shortened by that much.

[Brief explanation of the drawing]

1 and 2 are block diagrams and timing diagrams of one embodiment of the present invention, w43 diagrams and FIG. 4 are R of the conventional example.
2 is a block diagram and timing diagram of OM. FIG. 1.51...Chip enable input terminal, 2.
...Control circuit, 3.53...80M section,
4. s4゜55・・・Address latch,
5~8.57~60...address data input terminal, 9.64...memory data output terminal, lO~
13.65-68... Memory data output terminal, 1
4.69...Ready signal output terminal, 52...
...First control circuit, 53...Second control circuit, 61...Next address write signal input terminal. Bud 2 system

Claims (1)

[Claims] the address of the storage data to be read next during the reading period of the storage data of the address latched in either of the first and second address latches. A read-only memory characterized by latching in addition to the second address latch.