SU1226473A1 - Interface for linking information source with information receiver - Google Patents

Abstract

The invention relates to the field of computer technology and can be used to coordinate speeds when synchronously transferring data from a source to a receiver of information. The aim of the invention is to improve the speed of the device. The goal is achieved by the fact that the device containing the memory, the address switchboard group, the first write and read counters, two decoders, the AND element and the OR element, introduced the second write and read counters, a trigger, two comparison circuits, and the second AND element .I Il. with S (L N9 N5 O) Ch oo

Description

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The invention relates to the field of computing and can be used to coordinate the speeds for the asynchronous transfer of HiiK data from the source to the receiver of information.

The aim of the invention is to improve the speed of ycTpoficTBa.

The drawing shows the functional diagram of the device.

The device contains memory 1, switches 2 group addresses, decoders 3 and 4, first counters 5 and 6 write and read, trigger 7, comparison circuits 8 and 9, element OR 10, elements 11 and 12, groups of information inputs 13 and outputs 14, inputs 15 and 16 of the write and read strobes, outputs 17 and 18 of the write lock and read lock signals, outputs 19 and 20 of the decoders 3 and 4, second counters 21 and 22 of the write and read. Memory 1 contains a matrix of random access memory modules t (Mx1

The device works as follows.

In the initial state, the counters 5, 6, 21 and 22 and the trigger 7 are zero, the outputs of the comparison circuits 8 and 9 are excited, and the output 18 is output a read blocking signal. In addition, the single potentials of the first outputs 19 and 20, respectively, of the first 3 and second 4 decoders are derived from single potentials, preparing each column for recording and reading information. When a write pulse arrives at input 15, decoder 3 gates, and a single potential appears at first output 19 of decoder 3, which is connected to the first control input of switch 2 and memory models of the k-th column. Next, the contents of counter 5 through the first information input of the k-th switch 2 are fed to the address inputs of the memory modules of the k-th column and the first word arriving at the inputs 13 is entered into the first cell of the selected modules. Switching by the same pulse (slice) to the next state, counter 5 prepares the insertion of the second input word into the second cell, and so on. before filling all the M cells of the memory modules of the kth column. At the moment when the modules are shown filled, the counter 5 will overflow and the overflow pulse will carry a single 73J

Ninu in counter 21. With gztom, a single signal is obtained on the second 19, output 192 D and 3, prepared for recording information (k-1)

The 5th column of the memory modules 1. The recording of information in other memory modules 1 is similar.

Immediately after the first word is written into the first cell of the kth column of memory module 1 from output 18, the read lock signal is cleared. Since the counters 6 and 22 are in the zero state, the first word will be read into the information receiver.

5 to the first address of the memory modules of the 1st column. Each read pulse arriving at input 16 prepares the address of the next cell of these modules until the moment of reading.

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all words and counter overflow

6, and the overflow pulse puts the unit into counter 22. Next, the unit signal is scanned at (k -) - m output of the decoder 4, thus preparing (k-1) th column of memory modules 1. If the write and read information produced from the same memory modules 1, then writing is blocked when writing information

outputting a signal at output 18. If information is recorded and read from different memory modules 1, then writing and reading processes can be performed simultaneously. When the memory is full, i.e. when the overflow of the counter 21 is set to one trigger 7, fixing the recording of information in all memory modules 1. Further recording of information

the modules of the k-th column will again be produced, and if the recording of information advances the reading of information from memory 1 and the contents of counters 5, 21 will become equal to the contents

counters 6, 22, the circuits 8 and 9 of the comparison will operate, and a signal is generated at output 17, which serves to block the recording of information in memory 1. Thus, the device allows you to write and read information in the same memory modules, without waiting for the write and read information from different columns of the memory modules, write information in

previously read memory cells, without waiting for the moment of reading all the words from the memory, all this allows to increase the speed of the device.

In addition, the memory capacity of a device can be changed quite simply without changing its structure by eliminating or adding storage modules together with the corresponding switch, some counters and decoders.

Formula of Invention

A device for interfacing the source and receiver of information containing a memory whose information input groups and outputs are respectively groups of information inputs and outputs of the device, a group of address switches whose outputs are connected to a group of memory address inputs, first write and read counters the clock inputs of which are connected respectively to the inputs of the write and read gates of the device, the information outputs are respectively connected with the first and second information inputs by the group address switch, the first the second and second decoders, the outputs of which are connected respectively to the groups of inputs for controlling the write and read memory modes, the first AND element whose output is the output of the write lock signal of the device and the OR element whose output is the output of the read lock signal of the device - characterized by the fact that, in order to increase the speed of the device, second counts are entered into it5

Records and a read counter, a trigger, two comparison circuits and a BTopoii I element, with the information outputs of the second write counters and readings being connected respectively to the information inputs of the first and second decoders and the first and second inputs of the first comparison circuit, the equality output of which is connected to About the first input of the second element AND and the control input of the second comparison circuit, the first and second information inputs connected respectively to the information outputs of the first write and read counters, and the equality outputs to The first inputs of the OR element and the first element AND, the second input of which is connected to the trigger output, the single and zero inputs of which are connected respectively to the overflow outputs of the second write and read counters, clock inputs connected respectively to the outputs of the overflow of the first write and read counters, strobe the input of the first decoder is connected to the input gate of the recording device and the second input of the second element And the output connected to the second input

0 of the OR element, the gate input of the second decoder is connected to the input gate of the device reading, the outputs of the first decoder are connected to the first control inputs of the switches

group addresses, the second control inputs of which are connected to the outputs of the second decoder.

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Editor T. Kugrysheva

Order 2135/49 Circulation 671 Subscription

VNIIPI USSR State Committee

for inventions and discoveries 11303.5, Moscow, Zh-35, Raushsk nab., 4/5

Production and printing company, Uzhgorod, st. Project, 4

Compiled by V. Vertlib

Tehred V. Kadar Proof-reader S. Cherni

one,

Claims (1)

A device for interfacing a source and a receiver of information containing memory, groups of information inputs and outputs of which are respectively groups of information inputs and outputs of a device, a corpse of address switches, the outputs of which are connected to a group of memory address inputs, the first write and read counters, whose clock inputs are connected respectively, with the inputs of the strobe recording and reading devices, information outputs, respectively, with the first and second information inputs of the switch group addresses, the first and the second decoders, the outputs of which are connected respectively to the groups of inputs for controlling the write and read memory modes, the first AND element, the output of which is the output of the write lock signal of the device, and the OR element, the output of which is the output of the device read lock signal, characterized in that, with the purpose of increasing the speed of the device, the second account is introduced into it 1226473 4 write counters and a read counter, a trigger, two comparison circuits and a second AND element, and the information outputs of the second record and read counters 5, respectively, are connected to the information inputs of the first and second decoders and the first and second inputs of the first comparison circuit, the equality output of which is connected to 0 by the first input of the second element And and the control input of the second comparison circuit, the first and second information inputs connected respectively to the information outputs of ^{, 5} output counters of writing and reading, and the equality outputs to the first inputs of the OR element and the first AND element, the second input of which is connected to the trigger output, the single and zero inputs of which ²⁰ connected respectively to the overflow outputs of the second record and read counters, clock inputs connected respectively to the overflow outputs of the first counts of ²⁵ read and write counters, the gate input of the first decoder is connected to the input of the recording strobe of the device and the second input of the second element And, the output connected to the second input of 30 elements OR, the gating input of the second decoder is connected to the input of the reading gate of the device, the outputs of the first decoder are connected to the first control inputs of the switches 35 of the group address, the first control inputs of which are connected to the outputs of the second decoder.