SU1211737A1 - Memory access driver - Google Patents

Description

The invention relates to computing and is intended to control buffer memory in information processing devices with hierarchical memory organization.

The aim of the invention is to increase the reliability of the operation.

1 shows a functional diagram of the device; Figure 2 is the same as an associative memory block; in Fig. 3, the same unit for generating a call request.

The device contains an address register 1, an associative memory block 2, a buffer memory block 3, a memory block 4, registers 5 and 6, a group of 7 elements AND, a request request formation block 8, informational inputs 9, address 10, signs of replacing failed cells 11 , the sync pulse of recording information 12, the sign of the read mode of the device 13, the outputs of the information 14, the upper bits of the address of the buffer memory 15, the sign of exchange with the buffer memory of the device 16.

The associative memory block contains a group of 17 memory blocks and a group of 18 comparators.

The call request generation unit contains a group of 19 AND elements, an OR-NOT 20 element, an SH-21 element, an OR-NOT 22 element, and an AND 23 element.

Buffer memory 3 has a block structure and consists of L rows and K columns and has a capacity of L-K. data blocks. A block is an information quantum, one-to-one corresponding to the information in the main memory. The buffer memory is built on a partly associative principle, the column address is determined by the part of the address of the address coming from address register 1, the desired series is addressed by the result of associative search in block 2.

Memory 4 is designed to store information about the reconfiguration of the buffer memory 3. The capacity of L-K bits is organized: To words with the length of If bits. If the I and reconfiguration bits in the jth word is set, then the buffer memory block that is located. in the 1st row and the jth column is fixed, i.e. completely replaces some kind of main memory block (failed). The zero value of the reconfiguration bit allows the use of the corresponding bsgfernoy memory block.

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The first register 5 is designed to receive and store an elephant of information read from memory 4 (the size of the L bits).

The second register 6 is intended for fixing the result of an associative search in block 2 (the size of the L bits).

Recording information in registers 1.5 and 6, as well as determining the recording mode in block 4, is carried out by clock pulses (not shown in Fig. 1) by the level of a logical unit of a clock pulse. The period and duration of the clock pulses are determined by the duration of the delay of the circuit elements.

The device works as follows.

The address for accessing the RAM is fed to the address input of the device 10 (Fig. 1) and is stored in the address register I. The address portion defining the column address is simultaneously input to the low-order bits of the buffer memory 3 address of the block 2 and the address input of memory 4. The older part of the address from address register 1 is fed to the information input of block 2, which determines the presence or absence of the requested data in the buffer memory 3.

The younger part of the address goes to the memory blocks 17 of the group (Fig. 2), where one of the K columns is selected. The read L cells arrive at the inputs of the respective circuits 18, where they are compared with the upper part of the address. Result of associative search (signals

from the outputs of circuits 18 / are stored in the second register 6 and simultaneously arrive at the input of the higher bits of the address of the buffer memory 3, where the row is addressed. The read data is fed to the information input of the device 14. At the same time, information is read from block 4 remembered in first case 5.

Suppose that reads are performed and readable data is detected in the i-th row, i.e. The i-th bit of the second register 6 is set to one. . Then (fig. 3) on the 1st input of the element IPI-HE 22 there is a single signal, i.e. at its output there is a zero signal, which is fed to the second input of the element OR 21. During a read operation,

There is no unit signal at input 13 of the device, therefore, at the second input of the element I 23 there is a zero signal, from its output the first input of the element OR 21 also receives a zero signal. Therefore, from the output of the element OR 21 to the output 16 of the device receives a zero signal, indicating that access to the RAM is not necessary, since the requested data is detected in the buffer and output to the information output 14 of the device.

If a write operation is performed (a single signal at input 13 of the device and data is detected in the k-th row, then exactly the same as the second input of the OR 21 element receives a zero signal from the output of the OR-NOT 22 element. At the second input of the AND 23 element there is a single the signal, since the write operation is performed, so if the i-bit in register 5 is set to 1, then the inputs of the t-th element from the AND 19 group of elements contain single signals, i.e. a single signal at the output, which - and the input of the first element OR NOT 20 and produces zero A signal on its output, arriving at the first input of the element AND 23. Therefore, from the output of the element 23, a zero signal arrives at the first input of the second element OR 21, therefore, from its output, the device receives a signal indicating that the RAM access is not necessary, since the buffer memory replaces the given block of the main memory (the single value of the i-ro bit in the first register 5). If the | th bit of the first register 5 has a zero value, then the outputs of all elements of the And 19 element group contain zero signals, i.e., at the output of an element OR- NOT 20 is a single signal that arrives at the first input of the AND 23 element. Therefore, from the output of the AND 23 element, a single signal is received at the first input of the second element OR 21 and then at the output I6 of the request for the main memory of the device, indicating that RAM must be accessed during operation. x records.

If the data is not detected in the buffer, then all the bits of the second register have a zero value and, therefore, at the output of the OR-NOT 22 element, a single signal that passed the OR 21 element is output

16 devices, i.e. in this case, during a read or write operation, a request is made to access RAM. The second register 6 is output 15 for the purpose of addressing the buffer memory block by the information processing unit in the write operations when the data is in the buffer. The information in the buffer memory is recorded through the input 9 of the device.

If no data is found in the read operation in the buffer, then the data read from the RAM is buffered. The signals from the input 12 of the device are determined by a number of a buffer memory, where buffered information is placed. If the download goes to {- and p d "then a pulse arrives at the direct input of an element from the group of elements And 7

which either goes to the output of the element if the i-th bit of the first register is 5 at zero, or does not pass if the -th bit is at one. Next, entering the block 2 and the buffer memory 3, the pulse records and buffers the information from output 9 and writes the high-order part of the address from address register 1 to memory 17.

Consequently, if a block of buffer memory replaces a block of main memory, then another block cannot be buffered in it. Input 11 of the device is used to record buffer storage reconfiguration information into memory 4. The location of the data in the buffer memory 3 is fed to the device Bbocdn 15.

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Thus, if the information processing device has detected a failure of the main memory block, then it is possible to replace the failed block with the buffer memory block with which the work is going on, and calls to the failed main memory block are suppressed. buffer memory occurs during failover, i.e. is a dynamic procedure.

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Compiled by M.Ctuura;

Editor N.Shvydka Tehred T. Tupik: Proofreader E. Sirohman,

Order 6AI / 53 Circulation 673 Subscription

VNIIPI USSR State Committee for Inventions and Discoveries 4/5, Moscow, Zh-35, Raushsk nab. 113035

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Claims (1)

A MEMORY CONTROL DEVICE comprising an address register, a buffer memory unit and an associative memory unit, wherein the information input of the address register is connected to the address input of the device, the low-order output of the address register is connected to the address input of the associative memory unit, the information input and output of which are connected respectively to the output of the upper bits of the address register and the input of the upper bits of the address of the buffer memory block, the information input, the input of the lower bits of the address and the output of which Connected, respectively, to the information input of the device, the output of the least significant bits of the address register and the information output of the device, characterized in that, in order to increase the reliability of operation, two additional registers are introduced into it, a memory block, a group of AND elements and a request generation block, and the block the request form contains a group of AND elements, two OR-HE elements, an AND element and an element OR, and the output of the least significant bits of the address register is connected to the address input of the memory block, the information input and output of which are connected respectively to the input of the signs of replacing the failed cells of the device and to the information input of the first register ^ the output of the M- ^ th discharge of which is connected to the inverse input of the Mth element of the group And to the first input of the Mth element AND of the group of the request generation unit, the second * input and output of which are connected respectively to the output of the Mth discharge of the second register and to the Mth input of the first element And LI-HE § (M = 1, L, where L is the bit depth of the first and second register), the output of the second register is connected to the output of the upper digits of the address of the buffer memory of the device and to the input of the second element OR O-HE, the outputs of the first and second elements OR-HE are connected respectively to the first input of the AND element and to the first input of the OR element, the output and the second input of which is connected respectively to the output of the sign of exchange with the buffer memory of the device and to the output of the And element, the second input of which is connected to the input of the sign of the ^ write-read mode devices input sync oimpulsa recording apparatus is connected directly to inputs of AND gates group Mth output AND gate group connected to M-th inputs of the write control block of associative memory and a buffer memory unit address register clock terminal, a first and a second register connected to the input of clock pulses device. 1 1211737 2