SU1310899A1 - Storage with simul taneous reading of several layers - Google Patents

Abstract

The invention relates to computing and can be used for buffer data storage. The purpose of the invention is to increase the speed of the device. The buffer memory contains a block 1 of pulse shapers, a block 2 of comparison, elements EXCLUSIVE OR 3, an element OR 4, a shaper of 5 pulses, an address block of reading, including registers 7 of read addresses and decoders 8 of a read address, address block 9 of writing, including a register of 10 addresses records and a decoder of write addresses, a matrix of 12 memory cells 13, each of which consists of a storage element 14, elements 15 and 16, as well as a register 17 of written data, registers 18 of read data, inputs 19 and 20 of an address Records, inputs 21-24 read addresses. The device records data from register 17 into cells 13 selected by decoder 11 in accordance with the address code in register 10 recorded from inputs 19 and 20. The reading is carried out independently at several addresses written from inputs 21-24 into registers 7. At the same time The decoders 8 activate the corresponding memory locations 13, the data is written to the registers 18 and fed to the inputs of the device. The presence of block 2 and imager 5 ensures that data is recorded at the required address only in the absence of reading data at the same address. 4 il. i 00 with

Description

The invention relates to computing and can be used for buffer memory, and can also be used in information transfer systems.

The aim of the invention is to improve the speed of the device.

FIG. 1 shows a diagram of the proposed device; in fig. 2 and 3 - two possible modifications of the pulse shaper unit; in fig. 4 - temporary ditact recording impulse to one input of the corresponding group of elements I 15, to the other inputs of which input is fed

information from the register 17. From the outputs of the elements And 15, the information is copied into the corresponding memory elements 14.

At outputs 28-31 of the decoders 8, sampling resolution signals are generated that enable the passage of information.

Agram of the proposed device. Yu of the corresponding memory cell 13 through

The proposed device (Fig. 1) contains a block 1 of pulse formers, a block 2 of address comparison (including, for example, a group of elements AND 16 EXECUTIVE elements on the corresponding inputs 37-42 of registers 18. Moreover, at the outputs 28 and 29, the sample enable signals in the first direction are set, and LEVEL OR 3 and the OR element 4), form-, 5 strokes 30 and 31 - enable signals selector 5 pulses, address block 6 of readout, including registers 7 of read addresses and decryptors 8 of read address, address block 9 of record, including register 10 addr Soviet records, the decoder

ki in the n-th direction.

When cyclically changing the write address codes, the block 1 pulse shaper (Fig. 2) generates pulse recording signals at the output 25 on the front and rear

11 write addresses, a matrix of 12 cells 13 memory - 20 fronts of the lower bit of the address code, ti, each of which includes memories, because the change of the write code is one-digit element 14, element 15, elements are connected with front and rear fronts And 16, the register of 17 data to be written, the registers of 18 read data of the most significant bit. The delay element 46 is necessary in order for the pulse signal

Research institutes for sampling, entries 19 and 20 of the write address, 25 entries at output 25 were formed after

inputs 21-24 read addresses, input 25 of the pulse shaper unit 1, output 26 of the compare unit 2, output 27 of the driver of 5 pulses, outputs 28-31 of the decoders 8 read addresses, outputs 32-33

termination of transients at output 26 caused by a change in the address address code. Since the pulse shaper 48 generates a pulse at its output on the leading edge of the signal from the output of the de-encoder And the write addresses, the outputs 30 of the delay 46 ment, for getting 34-36 of the register 17 of the recorded data, the inputs 37-42 of the register 18 of the read data, the information outputs 43 -44 devices and information inputs 45 devices. Block 1 pulse shapers on the falling edge of the signal from the output of the delay element 46 is fed to the input of the second shaper 48 pulses through the element 47.

With an arbitrary change of address codes

sov contains a delay element 46, a recording element 35, the block 1 of the pulse shapers NOT 47, the pulse shapers 48 of the pulses and the element (Fig. 3) contain two shapers 48

pulses for each bit of the write address code that form a write pulse signal when any code bit changes

COP OR 49.

At the inputs 19 and 20 addresses of the recording device receives the address code of one of the cells 13

the memory into which the indo write address is written to the inputs 19 and 20.

formations. Moreover, the input 19 receives the younger digit of the address code, and the input

20-most significant bit. The inputs of the 21 and 22 receive the code of the 1st address, the inputs 23 and 24 - the code of the n-th address, and the inputs

21 and 23 receive the lower bits of the address code of the interrogated cells, and the inputs 22 and 24 receive the higher bits.

At the output 25 of the pulse shaper unit 1, a write pulse signal is generated, which arrives at the clock input of the pulse shaper 5.

From the output 26 of the unit 2 of the comparison, the output signal of the one by one comparison of the write address codes with the address code of choice 45 is sent to the input of the imaging unit 5 pulses

50

The device works as follows.

On the front of the changeable write address code at inputs 19 and 20 of the device unit 1, the pulse formers generates a write pulse signal at output 25, and at the leading edge of which the driver of 5 pulses, if present, has an enable signal at output 26 of comparison unit 2, generates a write clock pulse at output 27 , on the leading edge of which the addressable block 9 of the recording forms at one of its outputs (32 and 33), depending on the code of the write address on the inputs 19 and 20 of the device, a clock pulse of recording, on the leading edge of which is through matches. From the output 27 of the imaging unit 5 of the pulses 55, the current elements AND 15, to the corresponding input of the address block 9 of the recording enters the memory cell 13, the information from the outputs 34-36 of the recording direction register 17 is rewritten. Thus, recording intact recording pulse. With outputs 32 and 33 of the address block 9 entries come

a write clock pulse on one input of the corresponding group of elements I 15, on the other inputs of which the input is fed

information from the register 17. From the outputs of the elements And 15, the information is copied into the corresponding memory elements 14.

At outputs 28-31 of the decoders 8, sampling resolution signals are generated that enable the passage of information.

 corresponding cell 13 memory through

elements AND 16 to the corresponding inputs 37-42 of the registers 18. Moreover, at the outputs 28 and 29, the sample resolution signals in the first direction are set, and at the outputs 30 and 31 - the resolution signals are selected

the low-order fronts of the entry address code, since the change of the entry code is uniquely associated with the leading and trailing fronts

younger bit The delay element 46 is necessary in order for the pulse signal

 write output 25 formed after

termination of transients at output 26 caused by a change in the address address code. Since the pulse shaper 48 forms at its output a pulse at the leading edge of the signal from the output of delay element 46, to get it 5

0

The device works as follows.

On the front of the changeable write address code at inputs 19 and 20 of the device unit 1, the pulse formers generates a write pulse signal at output 25, and at the leading edge of which the driver of 5 pulses, if present, has an enable signal at output 26 of comparison unit 2, generates a write clock pulse at output 27 , on the leading edge of which the addressable block 9 of the recording forms on one of its outputs (32 and 33), depending on the code of the write address on the inputs 19 and 20 of the device, a clock pulse of recording, on the leading edge of which through the corresponding 5 st The elements AND 15 in the corresponding memory location 13 are rewritten information from the outputs 34-36 of the recording direction register 17. Thus, the recording of information in the memory cell 1.3 occurs after time T, after changing the code of the write address at the inputs 19 and 20 of the device. The time T is equal to the sum of the delays in the passage of the signal through the devices I, 5, 11, 15, and 14. With the modern element base, the time T is fractions of a microsecond.

With the inhibit signal at the output 26 of the unit 2 of the comparison, the shaper 5 of the pulses at the output 27 does not generate a write clock pulse. Thus, the recording of new information in the memory cell 13 at the time when a sample is taken from it, does not occur, and the reading of false information is excluded.

The information is sampled independently of each other in each of the directions. In this case, the decoders 8 of the readout address, using the codes in registers 7, generate signals at the corresponding outputs 28-31, through which information 16 is transmitted from the storage elements 14 of the matrix 12 to the registers 18 through the elements 16.

In the diagrams (Fig. 4), positions 26 and 25 show the states of the respective outputs, and positions 27-1 and 27-2 show the possible states of the output 27 of the controlled pulse generator 5.

At time tj-te; tg; t, the device operates in accordance with the described algorithm. In some cases, a pulse state occurs at the inputs of a controlled pulse shaper 5, resulting in 4 situations possible (times t ,, tj, t, and t).

The mismatched write and sample address codes are set and the pulse generator 5 to be controlled generates a write clock pulse (times t, and tj). The output state 27 corresponds to diagram 27-1. Recording and sampling operations are carried out with respect to the different memory cells 13.

Mismatched write and sample address codes are set, and the controlled pulse generator 5 generates a write clock (time t, and t). The output state 27 corresponds to diagram 27-2. There is a loss of information that must be recorded in this cell 13 of the memory.

Set the matching address and sample address codes and the controlled pulse generator 5 does not generate a write clock (times t and tj). The output state 27 corresponds to diagram 27-1. Information is not recorded in cell 13 of the memory from which sampling is made.

Matching write and sample address codes are set and the pulse generator 5 to be controlled generates a write clock pulse (times t, and tj). Output state 27 corresponds to

Figure 27-2. Since the newly recorded information is set at the outputs 43 and 44 of the device through time T after changing the code of the write address (time T is equal to the total delay of the signal passing through devices 1, 5, 11, 14, 15, 16 and 18), the sample of false information will be excluded if the reading of information with. the device outputs 43 and 44 will be performed after changing the sampling address after a time greater than 0 Tj.

Consider the worst case in terms of reliable sampling of information. Such a situation occurs at times t and tg, when the same write and sample address codes are set almost simultaneously and because of the signal status, the controlled impulse generator 5 generates a write clock (chart 27-2). Since the recording of information

0 occurs on the leading edge of the write clock pulse, then through time T after setting the write address code from the device outputs 43 and 44, reliable information can be retrieved from the memory location to which the recording is made. Due to the limited speed of electronic circuits in any memory device, including the prototype, such a delay between recording and sampling is necessary, i.e. the device ensures reliable operation

0 at maximum speed. The losses of the recorded information, possible at the moments of time t, and t (diagram 27-2) and tv and tj (diagram 27-1) are extremely rare and can be neglected. The main loss of recorded information occurs in

5 times t and tg (Figures 27-1 and 27-2).

Claims (1)

Invention Formula  A memory device with simultaneous reading of several words containing a matrix of memory cells, a register of data being written, registers of read data, read address address switches, a write address address switch, read address registers, a write address register, the first control inputs of the memory cells of each row of the matrix are connected to the corresponding output of the write address decoder, whose information inputs are connected to the outputs of the write address register whose outputs are the write address addresses of the device oystva, data inputs of memory cell columns of a matrix are combined and connected to the outputs of recordable data register inputs 5 of which are the information inputs of the device, the same control inputs of the memory cells of the matrix row are combined and connected to the outputs of the corresponding read address resolvers, input 0 The bounces of which are connected to the outputs of the corresponding read address registers, whose inputs are the addresses of the device read addresses, the same outputs of the memory cells of each of the matrix columns are combined and connected to the information inputs of the corresponding read data registers, the outputs of which are information outputs of the device, different that, in order to improve speed, the device contains a block of pulse shapers. a comparison unit and a pulse shaper, the output of which is connected to the gate input of the write address decoder, a clock input of the pulse shaper is connected to the output of the pulse driver, whose inputs are connected to the inputs of the write address register and to the inputs of the first group of the comparison unit, the inputs of the second group of which are connected to the inputs of the read address registers, the output of the comparison unit is connected to the enable input of the pulse former. / 7-2 4J Editor T. Parfenova Order 1763/49 Compiled by S. Shustenko Tehred I. VeresKorrektor I. Erdeyi Circulation 590 Subscription VNIIPI USSR State Committee for Inventions and Discoveries 113035, Moscow, Zh-35, Raushsk nab. 4/5 Production and printing company, Uzhgorod, ul. Project, 4 Compiled by S. Shustenko Tehred I. VeresKorrektor I. Erdeyi Circulation 590 Subscription