JPH0659111B2 - Time switch - Google Patents

Description

Description: FIELD OF THE INVENTION The present invention relates to a time switch used in a time division exchange or the like.

[Background of the Invention]

Conventionally, regarding a switching control method for increasing the speed of a time switch by using a memory circuit element having a comparatively slow cycle time, for example, “Bala, Hamasato, Inoue, Takahashi in“ Research Practical Report, Vol. 28, No. 7 (1979) ”. In "Documentation with Time Switch". Then, a parallel access method has been proposed in which sequential access is performed simultaneously, as opposed to a normal access method in which writing (writing) and reading (reading) are alternately performed.

According to this method, when the number of blocks is increased to some extent, the normal call memory access frequency per slot time can be reduced to about half, and the switch speed can be increased without increasing the memory capacity. It can be improved up to 2 times.

However, due to recent advances in semiconductor technology, it is economically difficult to increase the number of block divisions as the capacity of memory devices is gradually increasing.

[Object of the Invention]

An object of the present invention is to provide a time switch in which a relatively large capacity memory is used, the switching speed can be easily improved with a small number of blocks, and the delay time inside the switch is shortened. .

[Outline of Invention]

In order to achieve the above object, a memory element having a high-speed (for example, 1/2) cycle time may be used, but there is an upper limit for increasing the speed of the memory element.

Therefore, in the present invention, by using two sets of memory elements having the same cycle time, one for reading and the other for writing, and by alternately controlling the two memory elements, the upper limit of the memory elements is increased. The feature is that switching is possible in almost half of the cycle time.

Example of Invention

An embodiment of the present invention will be described in detail below with reference to FIGS. FIG. 1 is a block diagram of a time switch according to the present invention, in which 1 to 4 are speech path memories, 5 and 6 are (call control information) holding memories, 7 to 15 are flip-flops, and 16 and 17 are outputs. The control circuit, 18 indicates an inverting circuit, which is connected as shown.

FIG. 2 is a time chart for explaining the circuit operation of FIG. 1, and the circuit operation will be described together with the time chart.

In the time chart of FIG. 2, A to I indicate time slots A to I, R indicates a read cycle, and W indicates a write cycle. Also, w _{0 to} w ₄ , x ₀
~ X ₄ , y ₀ ~ y ₃ , z ₀ ~ z ₃ are flip-flops 12 ~
Shows 15 time slots.

First, from the terminal IN of FIG. 1, 8.192Mb / s, that is, 102
The four multiplexed parallel PCM signals are input and latched in the flip-flops 7, 8 to 11 every other slot time and alternately with a clock signal of 4 MHz as shown in FIG. At this time, for example, the flip-flops 8 and 10 and the flip-flops 9 and 11 are alternately arranged such that the flip-flops 8 and 10 latch data of odd time slots and the flip-flops 9 and 11 latch data of even time slots. Latch time slot data to.

The two holding memories 5 and 6 alternately repeat reading and writing, for example, when the holding memory 5 is in a read cycle, the holding memory 6 is in a write cycle.

The four call path memories 1 to 4 receive the call data from the respective flip-flops 8 to 11 according to the output of the counter (clock signal) and the command signal from the output control circuit 16 and the call path memories 1 and 2. And the channel memory
Sequential writing is performed alternately with 3 and 4. The channel memories 1 and 2 perform random reading according to the output data of the holding memory 6, and the channel memories 3 and 4 perform random reading according to the output data of the holding memory 5. Then, the flip-flops 12 and 13 are latched by the clock signal CLK ₁ , and the flip-flops 14 and 15 are clocked by the clock signal C
Latched by LK ₀ .

Next, the output control circuit 17 causes the flip-flop.
Select either 12 or 13 and either of flip-flops 14 and 15 alternately and output "1024" to output terminal OUT.
It is sent out as a multiplexed "8.192 Mb / s parallel PCM signal.

Here, in this method, one cycle 122ns (8.192M
b / s) read and write, but actually all the holding memory channel memory is 1 cycle 224ns
That means you are reading and writing. That is, with a memory with a cycle time of 244ns, one cycle is 122
A time switch of ns can be realized. This means that the switching operation is performed at half the cycle time of the upper limit of the memory device.

This point is explained by applying a little more numerical values. Since the PCM frame time is generally 125 μs, the relational expression T = 125 × 10 ⁻⁶ / n holds between the cycle time T and the multiplicity n. Here, the multiplicity n is “1024”.
In this case, the cycle time T is 122 ns, and the read cycle and the write cycle must be performed in 61 ns.

Therefore, a high-speed memory with an access time of 20 to 30 ns is required, but according to the present embodiment, since the read and write cycles can be performed at 122 ns each, an inexpensive general-purpose memory device with an access time of about 45 ns can be used. A circuit can be realized.

In the above embodiment, it is considered that one cycle is performed by reading and writing.

〔The invention's effect〕

As is apparent from the above-described embodiments, according to the present invention, two sets of memory circuits having the same cycle time are used, and one of them is for writing and the other is for reading, so that they are alternately operated. Since a time switch capable of high-speed switching can be realized and a general-purpose inexpensive memory element can be used, the economical effect is great. Further, there are advantages that it is highly expandable, has a high degree of freedom, and time switches of various speeds can be easily configured.

[Brief description of drawings]

FIG. 1 is a block diagram of the time switch according to the present invention, and FIG. 2 is a time chart for explaining the circuit operation of FIG. Is. 1 to 4 …… Channel memory 5,6 …… Holding memory 7 to 15 …… Flip-flop 16,17 …… Output control circuit

Claims (1)

[Claims] 1. A time switch comprising a call control information holding memory for random writing / sequential reading and a call path memory for sequential writing / random reading as main components, and an odd number on an incoming highway. Corresponding to the 1st and 2nd channel memory allocated to the time slot, the 3rd and 4th channel memory allocated to the even time slot on the incoming highway, and the 1st and 3rd channel memory The first call control information holding memory provided in common with the above, and the second call control information holding memory provided in common for the above second and fourth call path memories.
And the call control information holding memory, the first and third call path memories are alternately set to the write mode and the read mode for each time slot period as the same operation mode, while the second and fourth call path memories are set. The memory is a time switch configured so that it can be alternately placed in a read mode and a write mode for each time slot cycle as the same operation mode different from the operation modes of the first and third communication channel memories.