JPS59119996A - Time switch system using multi-port memory - Google Patents

Abstract

PURPOSE:To increase the capacity of a time switch without increasing the necessary speed nor the memory capacity of a channel memory by writing the information delivered from an incoming highway in parallel to the channel memory and then reading said information in parallel out of the channel memory to send it to each outgoing highway. CONSTITUTION:Writing ports WP1 and WP2 write independently and in parallel the write data wd1 or wd2 delivered from an incoming highway to memory units ME1-MEn designated by a write address wa1 or wa2 via gates G1-Gn. Then read ports RP1 and RP2 read out independently the data stored in the memory units ME1-MEn designated by a read address ra1 and ra2 and deliver the read data rd1 or rd2 to an outgoing highway.

Description

DETAILED DESCRIPTION OF THE INVENTION (al) Technical Field of the Invention The present invention relates to a time switch used in digital switching equipment, etc., and in particular to a time switch that is capable of independently operating a plurality of writing or successive addresses for one memory group. This paper relates to a time switching system using multi-board memory, which can be used to construct a large-capacity time switch.

(bl Technical Background FIG. 1 is a diagram showing an example of a time switch to which the present invention is applied. In FIG. 1, each write data Wd arriving from each communication path of the large highway HWi is After the write address Wa supplied from the counting circuit CN'I'' which advances in synchronization with the selection circuit SEL is written in the communication path memory SPM, the communication control is performed in synchronization with the communication path. f is read from each address of the information holding memory CM and is applied to the subsequent address ra supplied via the selection circuit SEL.
jt is read out from the speech path memory SPM and sent out as read data rd in each time slot of the outgoing highway HWO. By appropriately setting successive addresses ra stored in each address of the call control information holding memo IJcM, the write data w of each call path within the large highway HW i
d can be converted into the subsequent take rd of any communication path within the outgoing highway HW o. When configuring a call path network of a time division switch using such time switches, from the viewpoint of simplifying switching control and reducing internal congestion, the number of call paths within the incoming highway HW i and the outgoing highway HW o (hereinafter (referred to as highway multiplicity) is desirably as high as possible. However, as the highway multiplicity increases,
The required operating speed of the channel memory SPM also increases.

FIG. 2 is a diagram showing an example of the relationship between highway multiplicity and memory operating speed. In Figure 2, if the period of each communication path is 8 kilohertz, the highway multiplicity is 1000.
If the highway multiplicity is 2000, the memory operating speed will be 32 MHz. Therefore, the capacity of the time switch shown in FIG. 1 is limited by the memory operating speed.

fC) Differences from the Prior Art FIG. 3 is a diagram that does not show an example of a conventional time switch system. In FIG. 3, there are a plurality of incoming highways HWil and I-I Wi 2, and a plurality of outgoing highways HWo.
1 and HW o 2 are accommodated.

Write data wdl arriving from each communication path of the large highway HW i l is stored in a plurality of communication path memories SPMII and S
Write data wd that is simultaneously written to PM12 and arrives from each communication path of input highway HW i 2 in parallel.
2 is also written to the channel memories SPM21 and SPM22 at the same time. Channel memory SPMII and SPM21
Both write data wdl and wd2 stored in the call control information holding memory CMI are read out as appropriate by the read address ra1 supplied from the call control information holding memory CMI, and at the same time they are controlled by the switching signal s1 supplied from the call control information holding memory CMI. Output highway HW o via selection circuit SEL 1
The subsequent data rdl is sent to each communication path of l.

In addition, both write data wdl and Wd2 stored in the call path memories SPM12 and SPM22 are also stored in the read data 1ζ address ra supplied from the call control information holding memory l) CM2.
The output highway HWo
The data rd2 is sent to each communication path of 2 as successive data rd2.

If the highway multiplicity of the present highways HWil and HWi2 and the outbound highways HW o l and HWo2 are all 1000, the required operating speed of each communication channel memory SPMII to SPM22 is 16 MHz, as shown in FIG. Compared to the configuration (2000 multiplex), the required memory operation speed is halved. However, the channel memory S
The total storage capacity of PMII to SPM22 is doubled to 4000 call paths. If the number of incoming highways HWi and outgoing highways HW o is further increased, the communication route memory S
PMf7) The total storage capacity increases in proportion to the square of the number of communication paths.

As is clear from the above description, the conventional time switch system has the disadvantage that the storage capacity of the communication path memory SPM increases in proportion to the square of the number of communication paths.

(d+ Purpose of the Invention The purpose of the present invention is to eliminate the drawbacks of the conventional time switch method as described above, and to realize a large capacity time switch without increasing the required operating speed and storage capacity of the communication channel memory. exist.

tel Structure of the Invention The object of the present invention is to provide one or more write ports and read ports that can independently and simultaneously access each storage unit in a time switch for transmitting information arriving from an incoming highway to an outgoing highway by rearranging the order of arrival using a channel memory. configuring the communication route memory using a storage device having a boat, connecting a person highway to each of the writing boats, and connecting an outgoing highway to each of the following boats, thereby making it possible to connect the communication path memory to each of the writing boats, and to connect the outbound highway to each of the following boats; This is achieved by writing the information to the communication path memory in parallel, then reading the information from the communication path memory in parallel, and transmitting the information to each of the outgoing highways.

([1 Examples of the invention An embodiment of the present invention will be described below with reference to the drawings.

FIG. 4 is a diagram showing a multi-board memory according to an embodiment of the present invention, and FIG. 5 is a diagram showing a time switching method using a multi-board memory according to an embodiment of the present invention. Note that the same reference numerals indicate the same objects throughout the figures.

The multi-boat memory shown in FIG. 4 includes a plurality of storage units MEI to MEn, a plurality of write ports 1-WPI and WP2, and a plurality of read ports RP1 and RP2. Each write board 1-WPI and WP2 independently sends input write data wdl or wd2 to the storage units MEI to MEn specified by the write address wal or wa2 via gates G1 to Gn. It is possible to write by Further, each read port RPI and RP2 is connected to a memory unit MEI to MEn specified by the successive address ral or ra2, respectively.
The data stored in 81δ is output independently and in parallel,
It can be output as read data rdl or rd2.

This type of multi-baud memory allows a plurality of data to be written and read simultaneously, whereas conventional storage devices can only write or read a single piece of data at the same time. In FIG. 5, the multi-baud 1-memory shown in FIG. 4 is used as the channel memory SPM.

In FIG. 5, the write data wdl arriving from each communication path of the large highway HW r 1 is written from the write port 1-WP l
The write data wd2 arriving from each communication path of the input highway HWi2 is input to the write boat WP2. Each write boat WPI and WP2 receives write data wdl and w, respectively, according to write addresses wal and wa2 supplied from the counting circuit CNT.
d2 are written in memory units MEI to M E n simultaneously and in parallel. If the highway multiplicity of the modern highways HW il and HWi2 is each 1000, the required number n of memory units MEI to M E n is 2000, and the required operating speed is 8 MHz. On the other hand, the read ports RPI and RP2 each receive a subsequent address ra supplied from the call control information holding memory CM1 or CM2.
1 or ra2 specified 1.1 units ME1 to M
Write data wdl or wd written to IE n
2 are read out independently and in parallel, and the read data rd1 or r
d. Each exit highway HWOI or HWo as 2.
Output to each communication path of 2. If the highway multiplicity of each outgoing highway HWol and HWo2 is each 1000, the required operating speed of the storage units MEI to MEn is also 8 MHz.

As is clear from the above description, according to this embodiment, the communication path memory SPM uses a multi-board memory, so that the memory operation speed can be increased by 1 compared to the communication path memory IJ S P M shown in FIG. It is also possible to reduce the storage capacity to 1/2 and the memory operation speed to 1/2 compared to the communication path memories SPM11 to SPM22 shown in FIG.

Note that FIGS. 4 and 5 are only one embodiment of the present invention, and for example, the number of write ports WP and read ports 1-RP included in the multi-board memory, and the number of ports stored in the communication path memory SPM are shown in FIGS. The number of incoming highways and the number of outgoing highways are not limited to those shown in the drawings, and many other modifications may be considered, but the effects of the present invention will not change in any case.

In addition, the writing boards 1-WP 1 and WP2 and the reading boards 1-RP 1 and RP2 do not need to be dedicated ports, but a case where a shared port for writing and reading is used is also considered, but the present invention also applies in such a case. The effect of is unchanged. Furthermore, the highway multiplicity of the human highway HWi and the outgoing highway HW o, and the storage capacity of the communication route memo IJ S P M are not limited to those illustrated, and many other variations may be considered. Even in this case, the effects of the present invention remain the same. Furthermore, the configuration of the time switch, such as the relationship between the counting circuit CNT and the call control information holding memory CM, is not limited to that shown in the drawings, and many other modifications may be considered; However, the effect of the present invention remains unchanged.

(g+) Effects of the Invention According to the present invention, it is possible to realize a large-capacity time switch without increasing the required operating speed of the channel memory and the capacity described in 1.a.

[Brief explanation of drawings]

FIG. 1 is a diagram showing an example of a time switch to which the present invention is applied, FIG. 2 is a diagram showing an example of the relationship between highway multiplicity and memory operating speed, and FIG. 3 is a diagram showing an example of a conventional time switch method. FIG. 4 is a diagram showing a multi-board memory according to an embodiment of the present invention, and FIG. 5 is a diagram showing a time switch method using memory for multi-board 1 according to an embodiment of the present invention. In the figure, HWi, J (Wi 1 and HW i 2
Hairi Highway, I-IWo, HWo 1 and HW
. 2 is the exit highway, Sl) M, SPMII to SPM2
2 is a communication path memory, SEL, 5ELL and 5EL2 are selection circuits, CNT is a counting circuit, CM, CMI and 0M
2 is a call control information holding memory, MEI to MEn are
I unit, WPI and W'P2 are write ports, RP l
and RP2ba8 salebo1-1wd, wdl and w
a2 is write data, rd, rclL and ra2 are read data, wa, wal and wa2 are write addresses,
ra, ral, and ra2 do not indicate read addresses, and S1 and S2 indicate switching signals. 1st Figure 4 7/1 32 64 12gM
H! Memory Society Kai'F-dL Road Figure 2 Figure 3

Claims (1)

[Claims] In a time switch for transmitting information arriving from an incoming highway to an outgoing highway by rearranging the order of arrival using a communication path memory, one or more write ports 1- and successive ports that can independently and simultaneously access each position 1) and ii) are provided. By configuring the communication route memory using a storage device provided therein, connecting each of the writing boats to a person highway, and connecting each of the outgoing boats to an outgoing highway, A time switching system using a multi-board memory, characterized in that information is written in the jffi channel memory in parallel, then read out from the channel memory in parallel, and sent to each of the outbound highways.