SU1215134A1 - Device for initial setting of dynamic storage - Google Patents

Abstract

The invention relates to automation and computing and can be used in storage devices. The aim of the invention is to improve the speed of the device. The device contains the first and second multiplexers, a local control unit, a control unit, a row address counter, a column address counter, a frequency divider, a cycle counter, a regeneration generator. The device allows to reduce the time of initial installation of dynamic memory by controlling the recording in the memory in this mode with clock signals directly from the output of the regeneration generator. The presence of a cycle counter in the device allows the memory to be repeatedly assigned with initial information, 1 slug. (L

Description

The invention relates to automation and computing and can be used in storage devices.

The purpose of the invention is to increase the speed of the device, as well as to expand its functional capabilities.

The drawing shows a diagram of the device for the initial installation of dynamic memory.

The device contains the first multiplexer 1, address inputs 2, address outputs 3 of the first group, local control block .4, trigger 5, control block 6, second multiplexer 7, row address counter 8, column address counter 9, address outputs 10 of the second group, generator P regeneration, initial installation input 12, control input 13, equalizing outputs 14, frequency divider 15, counter 16 cycles.

The device for the initial installation of dynamic memory works as follows.

When the power is turned on, a reset signal is generated at the input 12 of the initial installation of the device, which sets all the device nodes to their initial state. The trigger 5 after setting to the initial zero state enables the device to operate in the initial memory installation mode.

After the reset signal is removed, the regeneration generator 11 starts operating, which pulses to the counting input of a frequency divider 15, designed to divide the frequency of the regeneration generator 11 in order to obtain the required regeneration frequency. In addition, the bits of the divider 15 frequency are used as high-order address bits that form the address code of the group (line) of the memory microcircuit in the drive. The address code is fed through the first multiplexer 1, controlled by the signal from the single output of trigger 5, to the address outputs of the first group 3 of the device. The pulse from the output of the regeneration generator 11 is fed to the input of the local control unit 4, which at the first output 14 generates the necessary sequence of signals, controlling the recording of information into the storage drive of the memory device

ten

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20

five

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va, and at the second output 14, the signals controlling the formation of the indicated information, for example, in the control node. At the address outputs 3 of the first device group and at the address outputs 10 of the second device group, a memory address code is generated. At the same time, at address outputs 10 of the second group of the device, the row address code is first generated, then the column chip address code of the memory chips, received through multiplexer 7, respectively, from the information outputs of the row address counter 8 and from the information outputs of the column address counter 9. The multiplexer 7 is switched using control signals sequentially generated by the control unit 6 under the influence of signals from the first output of the local control unit 4 and from the single output of the trigger 5. After the next output pulse is generated

25 regeneration generator 11 device using a frequency divider 15, a row address counter 8, a column address counter 9, a first multiplexer 1, a second multiplexer 7 generates 30 sledspmtsy cell address code

memory, and with the help of block 4, the local 5T1ravlenn again produces the necessary control signals.

Thus, the device allows recording information into all memory cells of the memory device. At the same time, in the initial memory setup mode, the signals necessary for the regeneration of information are not generated by the device, since it provides a frequency of accessing the lines of memory chips equal to the regeneration period. For normal operation of some memory chips, it is necessary to re-record information in the memory cells after turning on the power. In the proposed device, this is organized by means of a counter of 16 cycles, which sets the required number of prescription cycles. After filling the counter of 16 cycles, trigger 5 is set to one state, prohibiting the device to operate in the

55 initial installation. The device is re-: it goes into operation. In the operating mode, the control input 13 of the device receives a reversal signal and

40

45

the code of the operation to be performed. The address of the address is set at the address inputs 2 of the device. The local control unit 4, under the influence of the access signal and the code of the operation to be performed, arrives at the control input 13, as well as using signals from the single and zero outputs of the trigger 5, on the first, second and third outputs, the following signals: - control signals of the control unit 6, at the second output - a sequence of signals controlling the recording or reading of information from the storage device, at the third output - signals by which in the memory device ystve generated code number to an entry in storage or a fixed code Num la read from the storage means, depending on the operation to be performed. In the operation mode, the address code of the first line of memory microcircuits in the drive is formed at the address outputs 3 of the first group of devices, and the code of the address of the row and column of memory microcircuits is sequentially set at the address outputs 10 of the second group of the device. At the same time, this first 1 and second 7 multiplexers, under the influence of control signals, arriving respectively from the unit output of the trigger 5 and the output of the control unit 6, are switched by code from the address inputs 2 of the device. After performing the required operation, the local control unit 4 generates a response signal at the third output 14.

The regeneration control performed by the device is based on dividing the entire regeneration period into a number of regeneration cycles equal to the number of rows. During each cycle, one line is regenerated. The regeneration request signal, removed from the frequency divider 15, is fed to the local control unit 4, which at the first output generates the control signals of the control unit 6, and at the first output 14 generates the regeneration control signals in the memory storage device. The second multiplexer 7 switches to the third input from the information outputs of the row address counter 8. With

0 5 0 5 0

5 0 5

On the address outputs 10 of the second device group, the address code of the regenerated line is generated. After the regeneration memory has been executed, one is added to the counter 8 of the row address.

Claims (1)

Invention Formula A device for initial installation of dynamic memory containing the first multiplexer, the inputs of the first group of which are the inputs of the device, the outputs are the address outputs of the first group of devices, and the input of the sample is connected to the first input of the local control unit, the forward output of the trigger and the first the input of the control unit, the second input of which is connected to the first output of the local control unit, and the outputs are connected to the sample inputs of the second multiplexer, the inputs of the first and second groups of which are address inputs the devices, the inputs of the third and fourth groups are connected respectively to the information outputs of the row address counter and the column address counter, and the outputs are the address outputs of the second group of the device, the second and third inputs of the local control unit are connected respectively to the first output of the regeneration generator, and the inverse trigger output, the fourth input is connected to the R input of the trigger, the inputs of the regeneration generator, the row address counter and the column address counter and is the input of the initial setup of the device, the fifth the local control unit's stroke is the control input, and the second, third, and fourth outputs control the device outputs, the output of the row address counter is connected to the counting input of the column address counter, characterized in that, in order to increase speed, A frequency divider and a cycle counter are entered, the setup inputs of the frequency divider and cycle counter are connected to the initial setup input of the device, one output of the frequency divider is connected to the sixth input of the local control unit, and the others moves are connected to the inputs of the second group of the first multiplexer, counting input divide $ - 1215134 l frequency connected to the second output of the loop counter input connected the regenerator generator is connected, and the output to the overflow output of the counter overflow counter is connected to the counting column, and the overflow output from the row address counter counter is one with the S input of the trigger.