SU1377909A1 - Device for controlling data refresment in dynamic memory - Google Patents

Abstract

The invention relates to storage devices, in particular, dynamic-type operational storage devices, which are required to periodically access (restore or regenerate information) to save the information recorded in them. The aim of the invention is to simplify the device. The device contains synchronization unit 1, multiplexer 2 addresses, counter K 3 regeneration addresses, multiplexer 4 row addresses, trigger 5 (request for regeneration), trigger 6 (read cycle), regeneration trigger 7, trigger 8 (row select), shift register 9, one-bit memory block, elements 11-14, element 15, element 16, device 16 inputs and outputs. 4 il. S. &

Description

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about

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figure 1

The invention relates to storage devices, in particular, dynamic-type operational storage devices, which require periodic reference (retrieval or regeneration of information) to save the information recorded in them.

The aim of the invention is to simplify the device.

FIG. 1 shows a functional diagram of an information regeneration device in a dynamic memory unit; in fig. 2 - time diagram of the device; in fig. 3 - functional diagram of the block of synchronizing pulses; in fig. 4 is a timing diagram of the operation of the clock pulse block.

The device contains a block of synchronizing pulses, a multiplexer of 2 addresses, a counter of 3 addresses of regeneration, a multiplexer of 4 addresses of lines, a trigger 5 (request for regeneration), a trigger 6 (reading cycle), a trigger 7 (regeneration), a trigger 8 (choice of row), shift register 9, memory block 10 (one-bit), AND 11-14 elements, OR 15 element, HE element 16, address inputs 17, address outputs 18, command mode input buses 19, memory block control outputs 20.

Block 1 (Fig. 3) of the synchronizing pulses contains elements OR 21-24 elements AND 25-27, trigger 28 (start of a cycle) 5 trigger 29 (regeneration), trigger 30 (of a cycle), trigger 31 (initiation of a string), shift register 32 , elements And 33-35, clock generator 36.

The device works as follows.

Upon receipt of read or write commands to the inputs 19, the relay block of synchronizing pulses generates a signal at the second output that controls the connection of the address outputs 18 to the outputs of the multiplexer 2, and at the outputs 20 generates control signals for the operation of the dynamic memory. A more detailed operation of unit 1 is discussed below.

Multiplexer 2, depending on the signal at its control input, connects the output to the first or second input.

During the execution of read or write commands, unit 1 generates

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five

the third output signal at the fourth output is the start signal T of the cycle. At the same time, trigger 6 (reading cycle) is set to O and the signal through AND 14 and Element OR 13 removes a reset signal from the reset input of the shift register 9, which sequentially, starting with the first bit, begins to set 1 on each of its the outputs that are used to form the cycle of operation of the one-bit memory block 14 in the Read-Modify-Write mode.

After setting the first bit of the shift register 9, a trigger 8 (row selection) is established, connected to the row selection input of the one-bit memory block 10. After setting the third bit, the input for selecting the column is excited, after setting the nth bit, the record input. At the same time, at the information input of a single-bit memory block, O, and, to the address input, a multiplexer 4 of the row address switches the address outputs 18.

Thus, in parallel with the working accesses to the cells of the dynamic memory, zeros are written into the lines of the one-bit memory block 10 corresponding to the rows of the main dynamic memory.

I

The device uses the method

distributed regeneration. Unit 1, as shown below, generates signals at the first output with a Regeneration Request (TXP is the allowable storage time for information in the dynamic memory, n is the number of rows of the dynamic memory block).

With the arrival of the next signal, the Regeneration Request is added 1 to the counter 3 of the regeneration addresses, the contents of the cell with the address corresponding to the counter 3 (the regeneration address of the next line) are read from the one-bit memory block 10, and then 1 is written to this cell. From the one-bit memory block 10 reads O, it means that for the period a line with such an address was reversed and regeneration of this line is not required, if it reads 1, then a line regeneration is required ..

The operation is performed as follows (Figs. 1 and 2).

Signal Request for regeneration from the first output of block 1 sets the trigger 5 (request for regeneration). In this case, in the absence of a signal of the third output of block 1, 1 is set at the output of the element 11, which is fed to the single input of trigger 6 (reading cycle). If in

The units in accordance with the timing diagram in FIG. four,

In this case, B, in accordance with the timing diagram (Fig. 4), trigger 31 and elements 33 and 34, respectively, form dynamic memory chip control signals :, row excitation, column excitation.

Signal rem rem. Request reg-Q Record

If the work service is working reading and elements of rum input with O and

If the loop does not run, the dynamic memory operation cycle then the element NOT 16 blocks the second input of the element 11 before the end of the cycle.

After the trigger 6 is installed, the multi- 5 plexer 4 connects the output of the counter 3 to the address inputs of the one-bit memory block 10. At the same time, the And 11 element is blocked by the first input.

If trigger 29 was at zero (command service mode) in the fifth clock cycle of register 32, AND 35 generates a RAM response, upon receipt of which the input read or write command is removed. At the same time, through the elements OR 23, AND 27, W1 and 24 at the second input, the element AND 25 is set to O and TaKTOBbUi the impulse to the installation element OR 15 removes the signal that is reset to O, the trigger 28. Next

Sa from the shift register 9, which, as described earlier, forms the cycle of operation of the one-bit memory block 10 in the Read-Modify-Write mode.

When reading 1 into the element, And 12 sets 1 at the information input of trigger 7 (regeneration), and the pulse from the output of element 13 sets the trigger 7 to 1. At the end of the n regeneration cycle, unit 1 generates a signal at the sixth output, which resets the trigger 7. At When reading from the one-bit memory block 10, trigger 7 remains at zero.

The unit of the sync Tzoning pulses (Fig. 3 and 4) works as follows. I

When installing one of the signals

of a reference (Read or Write) or a regeneration signal T through the elements OR 21 and 22 appears 1 at the first input of element AND 25. If the previous cycle of the RAM is completed, then the other two inputs of element AND 25 are the same: 1 and the front of the pulse with The second output of the clock generator 36 is set to trigger 28 (the beginning of the cycle). From its front, the trigger 29 is set to command with no regeneration signal T at the input and into the regeneration state with a regeneration signal T present.

The front of the next clock pulse generator 36 sets the trigger 30 (cycle). This removes the reset signal from the shift register 32 and, starting at the next timepoint.

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The trigger pulse sets in O a trigger 30, which stores the register 32, closes And 27 and opens And 25 to receive the next reversal or regeneration signals.

When servicing the regeneration request circuit in the sixth cycle of the register 32 operation, element 26 through element OR 24 sets the second input of element AND 25 into o. In the future, the operation of the circuit is performed in the same way as when servicing the command.

The clock generator 36, in addition to the clock pulses at the second output, controlling the operation of the triggers 28, 30 and register 32, also produces at the first output the regeneration request signals with a period of Tour / n (T. P is the allowable storage time for information, n is the number of rows) .

Claims (1)

According to the invention, the next row regeneration cycle is skipped if, for the last time period T, p, this dynamic memory row has been accessed. Invention Formula A device for controlling the regeneration of information in dynamic memory containing an address multiplexer, the first information input of which is the device address input, a regeneration address counter whose output is connected to the first information input of the row address multiplexer and to the second information input of the address multiplexer whose output is connected to of the second pulse, it begins in the second information input milt Record If trigger 29 was at zero (command service mode) in the fifth clock cycle of register 32, AND 35 generates a RAM response, upon receipt of which the input read or write command is removed. At the same time, through the elements OR 23, AND 27, W1 and 24 at the second input, the element AND 25 is set to O and TaKTOBbUi impulse sets O to trigger 28. Next n 5 0 five 0 five The trigger pulse sets in O a trigger 30, which stores the register 32, closes And 27 and opens And 25 to receive the next reversal or regeneration signals. When servicing the regeneration request circuit in the sixth cycle of the register 32 operation, element 26 through element OR 24 sets the second input of element AND 25 into o. In the future, the operation of the circuit is performed in the same way as when servicing the command. The clock generator 36, in addition to the clock pulses at the second output, controlling the operation of the triggers 28, 30 and register 32, also produces at the first output the regeneration request signals with a period of Tour / n (T. P is the allowable storage time for information, n is the number of rows) . According to the invention, the next row regeneration cycle is skipped if, for the last time period T, p, this dynamic memory row has been accessed. Invention Formula A device for controlling the regeneration of information in dynamic memory containing an address multiplexer, the first information input of which is the device address input, a regeneration address counter whose output is connected to the first information input of the row address multiplexer and to the second information input of the address multiplexer whose output is connected to the row address plexus and is the address output of the device, a block of clock pulses, the output of the regeneration request signal of which is connected It is connected to the counting input of the regeneration address counter, the control output of the address output of the clock pulse unit is connected to the control input of the address multiplexer, Q and to the cycle signal output of the syncro15 20 The write and read inputs of the clock pulse block are the control inputs of the device, the outputs of the line excitation signal, the output of the column excitation signal, the output of the recording signal and the output of the response signal are the control outputs of the device, triggers, AND elements, the N1I element, the NOT element, different In order to simplify the device, it contains a memory block and a shift register, the reset input of which is connected to the output of the NL element, the first input of which is connected to the forward output of the 25 trigger, to the control input an ultiplexer of row addresses, to the information input of the memory block and to the first inputs of the first and second I elements, whose outputs are connected respectively to the D input and to the C input of the second trigger, the output of which is connected to the input signal of the regeneration request for the block synchronizing pulses, the second input element-IPI is connected to the output of the third element And, the first input of which is connected to the inverse output of the first trigger pulses, the output of the start of cycle signal of which is connected to To the input of the first trigger, the J input of which is connected to the output of the fourth element I, the clock input of the shift register is connected to the C input of the first trigger and to the output of the clock signals of the clock pulses, the output of the regeneration signal of which is connected to the reset input of the second trigger, first, the second, third, quarter and fifth outputs of the shift register are connected respectively to the C input of the fourth trigger, to the input selection column of the memory block, to the second input of the second element I, to the read input of the memory block and to the reset input black the right trigger whose output is connected to the memory row selector input, the address input and output of which are connected respectively to the output of the row address multiplexer and to the second output of the first And element, D-BXOJJM of the third and fourth triggers and the information input of the shift register are connected to the input of the unit logical signal device. (Pik.p.} regeneration- (ZS.§l.1} Ttsikl Tsanpocpes.s Tzi (lt. $ 8 lokpam, 10 Read „J1 record -.-- Read„ O, wnucb ,, Tregener, 7 79096 and the reset input of the third trigger, the C input and output of which are connected respectively to the first output of the clock pulses and to the first input of the fourth And element, the second input of which is connected to the output of the NOT element, the input of which is connected to the second input of the third And element five 0 5 ep pulses, the output of the start of cycle signal of which is connected to To the input of the first trigger, the J input of which is connected to the output of the fourth element I, the clock input of the shift register is connected to the C input of the first trigger and to the output of the clock signals of the clock pulses, the output of the regeneration signal of which is connected to the reset input of the second trigger, first, the second, third, quarter and fifth outputs of the shift register are connected respectively to the C input of the fourth trigger, to the input selection column of the memory block, to the second input of the second element I, to the read input of the memory block and to the reset input black the right trigger whose output is connected to the memory row selector input, the address input and output of which are connected respectively to the output of the row address multiplexer and to the second output of the first And element, D-BXOJJM of the third and fourth triggers and the information input of the shift register are connected to the input of the unit logical signal device. FIG. 2 Tregenets Ctie 3ani / i t Request reeroutment Request regeneration T2V (NO1.cycla) 723 (regeneration ШЖШдар1ЫШ1ги 11№ J L L 1eenerc.K26 signal JHSif record) J Editor N.Slobod nickname Uz.ff Compiled by S. Shustenko Tehred M. Khodanich Proofreader L. Pilipenko Signal Regener-. (0 / kshzshaa J L S g