JP2548206B2 - Semiconductor memory device - Google Patents

Description

Description: BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor memory device, and more particularly, to a refresh operation in a one-transistor dynamic random access memory (hereinafter referred to as DRAM) which requires a refresh operation. The present invention relates to a circuit configuration including a circuit that generates a necessary address.

2. Description of the Related Art In recent years, semiconductor integrated circuits have become highly functional and
In AM as well, high functionality and multi-functionality have been carried out in order to make it easier to use with higher integration. Especially in a DRAM with a one-transistor type memory cell, since information is stored as charges accumulated in a capacitor,
Since it is necessary to prevent the loss of information due to changes over time, the refresh operation must be performed at regular intervals. The refresh operation is performed by performing a normal read operation on the memory cell connected to the word line selected by the row decoder, thereby amplifying the information in the memory cell on the bit line and rewriting. This operation in a certain time
By selecting and executing all word lines of DRAM,
A refresh operation can be performed on all memory cells.

At that time, a row address for selecting a word line is input from an external address input terminal when a row address strobe (hereinafter referred to as ▲ ▼) is input. However, the column address strobe (below ▲ ▼
And the phase relation between ▲ ▼ and ▲ ▼ are reversed from the case of normal read operation and write operation, and the refresh operation is performed by using the output from the built-in address counter as the row address for refresh.
▼ Refresh has become widely used.

The conventional circuit for performing the before-refresh will be described below.

FIG. 3 shows an example of a conventional circuit for before-refresh, and FIG. 4 schematically shows the waveform of each node in the circuit of FIG.

In FIG. 3, reference numeral 1 is the first activated by the input
A timing generator, 2 is a second timing generator activated by an input from the first timing generator 1 and 3 is an output from the first timing generator 1 and an input from the first timing generator 1. A circuit for performing a phase comparison between the ▼ input and the ▲ ▼ input, 4 is a third timing generator activated upon receiving an output according to the comparison result in the phase comparison circuit 3, and 5 is a third timing generator 4 It is a counter for generating an internal address signal controlled by. 6
Is a row address buffer drive circuit controlled by the third timing generator 4, 7 is a row address buffer controlled by the drive circuit 6 in response to an external address input signal or the output of the internal address counter 5, and 8
Is a row decoder which receives the output from the row address buffer 7 and selects a word line, and 9 is a word line drive circuit which is controlled by the timing generator 1 to drive the word line selected by the row decoder 8. is there. Also, 10
Is a column address buffer drive circuit controlled by the second timing generator 2, and 11 is a column address buffer controlled by the column address buffer drive circuit 10 in response to an input signal from the external address signal input terminal.
Note that only one row address buffer, one column address buffer, one address counter, and one row decoder are shown in FIG. 3, but each has a number determined by the memory capacity, word structure, and address structure. Is.

In FIG. 4, during the period (a), ▲ ▼ and ▲
Since the phase relationship of ▼ is the case of a normal read operation or write operation, an output according to the result of this phase relationship is transmitted from the phase comparison circuit 3 to the third timing generator 4, and the external address input signal is transferred to the row address. Input signal φ _{1 of} the transfer gate transmitted to the buffer 7.
Becomes high level, and the input signal φ ₂ of the transfer gate transmitting the output of the internal address counter 5 becomes low level. Then, after ▲ ▼ falls, the row address buffer drive circuit 6 drives the row address buffer 7
The input signal φ ₀ of the transfer gate to the low level becomes low level, and the external address input signal AO ₁ is taken into the row address buffer 7. Also, regarding the column address,
Column address buffer drive circuit 10 after ▼
Input signal phi _'0 of the transfer gate to the column address buffer 11 becomes a low level, the external address input signal AO ₂ is taken into the column address buffer 11 by.

On the other hand, in the period of (b) of FIG.
The phase relationship between ▼ and ▲ is opposite to the period of (a), and ▲ ▼ is falling before ▲ ▼ is falling. In response to the output from the phase comparison circuit 3 that has detected this phase relationship, the third timing generator 4 sets φ ₁ to low level and φ ₂ to high level, and sets the address taken in by the row address buffer 7 to the external address input signal AO ₃
To output AI ₂ from the internal address counter. Further, the third timing generator 4 inactivates the second timing generator 4 and controls so that the column address buffer drive circuit 10 and the subsequent circuits do not operate. Therefore, φ _'0 will not be accepted address from the outside becomes a low level. Then, the internal address counter 5 is driven to advance the value of the counter 5 by 1 bit to prepare for the next (before) refresh. In this way, the output from the row address buffer 7 that has received the output from the internal address counter 5 selects the word line to be refreshed in the row decoder 8, and the word line drive circuit 9 selects the selected word line. The memory cell connected to this word line is driven to perform a refresh operation.

Problems to be Solved by the Invention In the conventional method as described above, the address counter for generating the internal address signal in refresh is intended only for refreshing all the memory cells, so that the refresh cycle is performed a fixed number of times. , I could only get a counter output that could drive all word lines. Therefore, although the refresh operation can be started from outside the DRAM, it is not possible to specify which word line inside the DRAM to start the refresh operation, so that the address counter malfunctions in the refresh operation by the internal address. And malfunctions related to word line drive,
There was a problem that it was difficult to clarify from outside the DRAM.

In addition, when performing a normal read operation or write operation after refreshing with an internal address,
If only ▲ ▼ is operated cyclically while keeping the state of rising, it is possible to respond by inputting only the column address to a plurality of memory cells connected to one word line. High-speed operation is possible without requiring the time required to fetch the row address and select the word line by ▲ ▼. However, there is a problem in that it is necessary to newly input a row address from the external address terminal because it is not possible to know what row address the word line selected by the refresh by the internal address corresponds to. there were.

The present invention solves the above-mentioned conventional problems, and when the refresh operation by the internal address counter is performed, the output of the address counter can be set from the outside, whereby the refresh operation by the internal address counter can be performed. (EN) Provided is a semiconductor memory device capable of facilitating clarification of a related defect and enabling control of an address for starting a high-speed read operation or write operation immediately after a refresh operation by an internal address counter. To aim.

In order to achieve this object, a semiconductor memory device of the present invention has an internal control clock generating circuit having a row address control clock and a column address control clock as input signals, and the internal control clock. An internal address counter circuit for generating an internal address signal by an output from the generating circuit; and an internal control signal generating circuit for generating an internal control signal by an output from the internal control clock generating circuit and a pulse signal applied from an external terminal. , An internal address counter output setting circuit for initializing the internal address counter circuit by the output from the internal control signal generating circuit.

Operation With this configuration, when the refresh operation by the internal address counter is started, it is possible to perform control so that the refresh can be started from the memory cell connected to the word line corresponding to the row address input from the external address terminal. By relating the number of refresh cycles to the number of progressing row addresses by facilitating the elucidation of related defects, the column address can be input without the need to input the row address from the external address pin immediately after refreshing by the internal address counter. It is possible to realize high-speed read operation and write operation for an arbitrary memory cell.

Embodiment One embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows a circuit structure for performing a refresh operation of a semiconductor memory device according to an embodiment of the present invention, and FIG. 2 schematically shows waveforms of respective nodes in the circuit of FIG. Note that the DRAM using the address multiplex method is illustrated here.

In FIG. 1, ▲ ▼ is a row address strobe signal input terminal, ▲ ▼ is a column address strobe signal input terminal, An is an external address signal input terminal, and EXT.
Is an input signal terminal (for example, a write enable signal input terminal or a data input terminal) in a don't care state during the refresh operation. 1 is the first timing generator activated by the ▲ ▼ input,
Reference numeral 2 denotes a second timing generator activated by an input and an output from the first timing generator 1, and reference numeral 3 denotes an output from the first timing generator 1.
A circuit for performing a phase comparison between the ▲ ▼ input and the ▲ ▼ input by using the ▼ input, 4 is a third timing generator activated upon receiving an output according to the comparison result in the phase comparison circuit 3, Reference numeral 5 is a counter for generating an internal address signal controlled by the third timing generator 4. Reference numeral 6 is a row address buffer drive circuit controlled by the timing generator 1, and 7 is a row address buffer controlled by the drive circuit 6 in response to an input signal from an external address signal input terminal or an output from the internal address counter circuit 5. Numeral 8 is a row decoder which receives an output from the row address buffer 7 to select a word line, and numeral 9 is controlled by the first timing generator 1 to drive the word line selected by the row decoder 8. It is a word line drive circuit. Further, 10 is a column address buffer drive circuit controlled by the second timing generator 2, and 11 is a column address buffer controlled by the drive circuit 10 in response to an input signal from an external address signal input terminal. An internal address counter output setting circuit 12 receives a signal from the EXT terminal and is controlled by the third timing generator 4. The address buffers, counters, and decoders are provided in the required number of memories.

The operation of the semiconductor memory device of this embodiment configured as above will be described. First, shown in FIG. 2 (A)
In the period of, so-called ▲ because ▲ ▼ is falling before the rising of ▲ ▼
▼ Before ▲ ▼ It is in a refreshing state. Therefore, the phase comparison circuit 3 transmits the output corresponding to the phase relationship of the second timing generator 2 to the timing generator 4. In response to this, the third timing generator 4 inactivates the second timing generator 2 and controls so that the column address buffer drive circuit 10 and the subsequent circuits do not operate. Therefore, φ ′ ₀ becomes low level and an external address is accepted. I can't. Further, φ _{1 is set} to low level and φ _{2 is set} to high level so that the output from the counter 5 is input to the row address buffer 7. At this time, since the pulse signal is input from the EXT terminal, the internal counter 12 output setting circuit is activated and controlled by the third timing generator 4 to set φ ₃ to the high level and the input signal AO ₀ from the external address terminal An To the internal address counter circuit 5 and controls the internal address counter circuit 5 so that the output AI ₁ from the counter becomes the same as AO ₀ . Further, the third timing generator 4 sets φ ₁ to low level and φ ₂ to high level so that the address signal received by the row address buffer 7 becomes the output AI ₁ from the internal address counter circuit 5. Then, the row address buffer 7 receives the input signal from the internal address counter 5 due to φ ₀ which becomes low level after ▲ ▼ falls.
The output is transmitted to the row decoder 8 so as to select the word line corresponding to AI ₁ . The word line selected in this way is activated by the word line drive circuit 9, and the refresh operation is performed on the memory cell connected to this word line.

Next, in the period of (B) of FIG.
Has risen and then has fallen again, ▲
Since ▼ is still falling, it is in the ▲ ▼ before ▲ ▼ refresh state as in the period (A). However, since the pulse signal is not input to the EXT terminal, the internal counter output setting circuit 12 is not activated, and φ ₃ remains at the low level. Therefore, the internal address counter circuit 5 operates in the period (A). Generates output AI _2, which is one bit advanced from output AI ₁ . Then, the refresh operation similar to that in the period (A) is performed on the memory cells connected to the word line corresponding to the address of AI ₂ .

Then, in the period of (C) of FIG.
While ▼ rises and then falls again, ▲ ▼ remains falling, so ▲ ▼ and ▲ ▼ show the phase relationship when performing a normal read or write operation. become.
The phase comparison circuit 3 which has detected this phase relationship transmits the output corresponding to this phase relationship to the timing generator 4, and the timing generator 4 which receives this outputs sets φ ₁ to high level and φ ₂ to low level. . However, ▲
Since ▼ remains falling, the word line whose address corresponds to AI ₂ selected in the period (B) remains activated. Further, when ▲ ▼ falls, the second timing generator 2 is activated, the column address buffer drive circuit 10 is controlled, and φ ′ ₀ , which was high level when ▲ ▼ rises, is changed to low level and the external address terminal is used. The input signal AO _{4 of} is input to the column address buffer. In this way, AO in the memory cell connected to the word line corresponding to the address of AI ₂
It becomes possible to access the address corresponding to the address of ₄ at high speed without the time required to fetch the row address and select the word line.

As described above, according to this embodiment, when refreshing by the internal address counter, it is possible to arbitrarily set the row address for refreshing by the internal address counter from the external address input terminal before the refresh is started. In addition, it is possible to easily clarify the cause of the defect related to the refresh operation using the internal address counter. When a read operation or a write operation is performed immediately after refreshing by the internal address counter, the word line corresponding to the address advanced by n-1 bits from the initially set address with respect to the number n of refresh cycles is selected. It is known that the memory cell can be accessed at high speed by inputting only the column address.

In this embodiment, the DRAM which can be refreshed before and after is exemplified. However, if it has an internal address counter circuit, it does not have a refresh control signal input terminal or an address multiplex system. However, even if it is provided with 12 internal address counter output setting circuits in FIG. 1, it can be easily applied.

According to the present invention, by providing the internal address counter output setting circuit, the output of the internal address counter is arbitrarily set from the external address input terminal depending on the presence / absence of a signal to the external input terminal in the don't care state when refreshing. This makes it possible to easily clarify defects related to the refresh operation by the internal address counter, and obtain an effect that the read or write operation immediately after the refresh by the internal address counter can be performed at high speed. An excellent semiconductor memory device can be realized.

[Brief description of drawings]

FIG. 1 is a circuit configuration and a circuit diagram of a semiconductor memory device according to an embodiment of the present invention, FIG. 2 is a schematic diagram of the waveform of each node in FIG. 1, and FIG. 3 is a circuit of a semiconductor memory device according to a conventional system. The configuration and circuit diagram, and FIG. 4 are schematic diagrams of the waveforms of the nodes in FIG. 1,2,4 ... Timing generator, 3 ... Phase comparison circuit, 5 ... Address counter, 6,10 ... Address buffer drive circuit, 7,11 ... Address buffer, 8 ... Row decoder, 9 ... Word line drive circuit, 12 …… Counter output setting circuit, ▲ ▼, ▲ ▼, ▲ ▼, An…
External input terminals, φ ₀ , φ ′ ₀ , φ ₁ , φ ₂ , φ ₃ ... Circuit nodes.

Claims (1)

(57) [Claims] 1. An internal control clock generating circuit having a row address control clock and a column address control clock as input signals, and an output which is changed in response to an output from the internal control clock generating circuit to generate an internal refresh address signal. Generated by an internal address counter circuit and a pulse signal input from an external terminal, and in response to an output from the internal control clock generation circuit, an external address terminal is input to the internal address counter circuit. A semiconductor memory device having an internal address counter output setting circuit for initializing an output according to a row address.