JPS6413293A - Semiconductor storage device - Google Patents

Abstract

PURPOSE:To facilitate the clarification of failure concerning with REF operation and to control an address starting high-speed read and write operation immediately after the REF operation by providing an internal address counter (IAC) output setting circuit. CONSTITUTION:Under the states of the before inverse of CAS and the inverse of RAS state, a phase comparator 3 transmits output complying with the phase relation of a second timing generator (TG) 2 to a TG 4. The TG 4 does not activates the TG 2 to prevent a column address buffer driving circuit 10 and subsequent circuits from being operated. Then phi0 goes to L and an external address is not accepted. Besides, the output of an address counter 5 is inputted to a row address buffer 7 by allowing phi1 to be L and phi2 to be H. At this time, the counter output setting 12 is activated by a pulse signal from an EXT terminal, an input signal A0 from a terminal An is transferred to a GT 5 by allowing phi3 to be H and the output of the A1 and A0 are equalized. Besides, an address signal received by the buffer 7 is equalized to the A1 by allowing the phi1 to be L and the phi2 to be H. Then the buffer 7 sends output selecting a word line complying with the A1 to a row decoder 8 and a word line driving circuit 9 executes the refreshment operation.