KR0172359B1 - Method of accessing to the fast data of semiconductor memory device - Google Patents

Abstract

1. The technical field to which the invention described in the claims belongs:

The present invention relates to a high speed data access method of a semiconductor memory device.

2. The technical problem the invention is trying to solve:

The present invention provides a high-speed data access method of a semiconductor memory device having a speed improvement of tRAC by performing a low address setup and decoding operation in a precharge section of a low address strobe clock RASB in a data access time tRAC form. Is in.

3. Summary of the Solution of the Invention:

The present invention provides a high speed data access method of a semiconductor memory device, wherein the low address strobe clock is input from the outside of the chip to a low address strobe buffer in a logic high state to output a low address input control signal to the low address input buffer. And a second process of outputting the low address buffered to the low decoder and the first control signal generator after a predetermined time by the low address input control signal while the low address strobe clock is at a logic high. And a third process of operating the low address strobe clock in a logic high state to output the decoded low address by performing a decoding operation on the low decoder in response to the low addresses generated in the low address input buffer. After a predetermined time of the third process operation. A fourth process in which the low address strobe buffer generates a second control signal when the low address strobe clock is in a logic low state, and controlled by the second control signal after a predetermined time of operation of the fourth process A fifth process of decoding the low addresses by the first control signal generator and outputting a first control signal; and by the decoded low addresses and the first control signal output from the low decoder and the first control signal generator. A sixth process of operating a word line driver to select a corresponding word line is included.

4. Important uses of the invention:

It is suitably used.

Description

High Speed Data Access Method of Semiconductor Memory Device

1 is a block diagram of a data access process according to the prior art.

2 is an operation timing diagram of FIG.

3 is a block diagram of a data access process according to the present invention.

4 is an operation timing diagram of FIG.

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to a low address high speed data access method.

In the process from the conventional Low Address Strobe Clock (RASB) input to the Low Address being applied to the Word Line, the low address input from the outside of the chip is set up. The method of operating up to the row select signal driver (hereinafter referred to as word line driver) by the operation of the RASB circuits by the logic low state of the low address strobe clock RASB is performed. Fig. 1 is a block diagram showing a low address input and word line driving process according to the prior art.The configuration and operation of the first embodiment are as follows: First, the logic low state of the low address strobe clock RASB is a low address strobe buffer 10. RAS circuit control clocks and low address input control signals by these clocks are generated when the signal is input to. The low address input unit (hereinafter referred to as low address input buffer 20) is operated by the generated low address input control signals, and at this time, the low address is received into the chip to generate the low addresses RAi and RAiB, that is, the clock RASB. Is in the logic high (High) state, even if the low address is input to the low address input buffer 30, the input buffer does not operate and the low address is not accepted into the chip.The low addresses RAi and RAiBs generated in the low address input buffer are free. It is input to the low decoder 40 via a decoder (Pre-Decoder), and part of it is input to the secondary decoder (hereinafter PXi generator 30), and the output of the low decoder selected by the low address and the output of the PXi generator 30. The word line driver 50 is activated by the PXi, which enables the word line.

The operation state described above is shown in FIG. 2 as the operation timing of the internal signal.

2 is an operation timing diagram of FIG. Referring to FIG. 2, the timing of receiving the low address is controlled by the low address input control signal PIB generated by the falling edge of the clock RASB, and the low address predecoding, low decoder, and PXi generator Operation takes place within the activation cycle (logical low state) of the clock RASB. Therefore, this causes various problems. First, the time of setting up the low address is determined by the low address input control signal PIB which occurs when the clock RASB goes logic low unlike the low address setup time outside the chip. Lose. Therefore, even if the low address setup is performed earlier than the time when the clock RASB becomes the logic low state, the actual address is set up at the polling time of the clock RASB so that the access time is lost. Second, by setting up the low address in the activation cycle of clock RASB to operate the predecoder, low decoder, and PXi generator, this operation speeds up the first latency, that is, the data access time (tRAC) from the clock RASB. Restricted Third, since the speed improvement of the tRAC is limited by the aforementioned reasons, the rising of the column address strobe clock (CASB) in clock RASB polling at page mode cycle timing is performed. There is a problem in that the time until t) (hereinafter, tCSH) is also limited to speed up.

Accordingly, an object of the present invention is to perform a low address setup and decoding operation in a data access time tRAC type in a precharge section of a low address strobe clock RASB, thereby increasing the speed of the tRAC. In providing an access method.

Another object of the present invention is to provide a high speed data access method of a semiconductor memory device capable of reducing the time tCSH from polling of the low address strobe clock RASB to rising of the clock CASB in a page mode cycle.

The technical idea of the present invention to achieve the above object is to buffer the low address strobe clock from the outside of the chip in the low address strobe buffer to send to the low address strobe circuit, and the address signal from the outside of the chip low A semiconductor memory device including an operation inputted to an address input buffer and buffered by an input control signal of the low address strobe buffer, and decoding the buffered address signal through a low decoder and a secondary decoder to activate a word line A high speed data access method according to claim 1, wherein the low address strobe clock is input from the outside of the chip to a low address strobe buffer in a logic high state to output a low address input control signal to the low address input buffer; As above A second process of outputting a low address buffered to the low decoder and the first control signal generator after a predetermined time by the low address input control signal in a state where the address strobe clock is logic high, and the low address strobe clock A third process in which the low decoder performs a decoding operation and outputs a decoded low address in response to the low addresses generated in the low address input buffer during a logic high state; and during operation of the third process A fourth process of generating a second control signal by the low address strobe buffer when the low address strobe clock becomes a logic low state after a time; and by the second control signal after a predetermined time of operation of the fourth process A first control signal by decoding the low addresses by the controlled first control signal generator A fifth process of outputting a call; and a sixth process of selecting a corresponding word line by operating a word line driver by a decoded low address and a first control signal output from the low decoder and the first control signal generator. It is done.

DETAILED DESCRIPTION A detailed description of preferred embodiments of the present invention will now be described with reference to the accompanying drawings.

It should be noted that like elements and parts in the figures represent the same numerals wherever possible.

3 is a block diagram of a data access process according to the present invention. Referring to FIG. 3, the configuration and the operation state are simultaneously described. When the clock RASB, which is the precharge start point of the low address strobe clock RASB, becomes high in logic high state, the low address is caused by the operation of the RASB buffer 60. The input control signal PIB is generated. In addition, the low address input unit, for example, the low address input buffer 70 operates by the low address input control signal PIB generated above when the clock RASB becomes logic high, and is received into the chip. Therefore, after the low address is latched inside the chip, the low address input control signal PIB is disabled to eliminate power consumption by operating the low address input buffer 70 within the precharge period of the clock RASB. The low addresses RAi and RAiB generated by the operation of the low address input buffer 70 are predecoded by a predecoder (not shown), and the predecoded output signal is input to the low decoder 90 to the low address outside the chip. The output signal of the corresponding low decoder is output.

In addition, some of the low addresses RAi and RAiB generated in the low address input buffer 70 are input to the secondary decoder (hereinafter, referred to as PXi generator 80) to select a signal PXi corresponding to the low address after a predetermined time delay. Therefore, the PXi generator is not operated within the precharge period (logical high state section) of the clock RASB.

As in the above operation, in the prior art, the operation of the low address input buffer 70, the pre-decoding operation, and the low decoder 40 performed in the activation cycle of the clock RASB (the interval of the logical low state) are described in the present invention. Operate in precharge section. In the next operation, the secondary decoder control signal PPXi is enabled when the clock RASB, which is the starting point of the activation of the clock RASB, becomes logic low. The PXi generator 30 is operated by the secondary decoder control signal PPXi. Is enabled and the word line is activated. Therefore, in the related art, the access process starts from the time point at which the clock RASB is logically enabled and the word line is activated only after a predetermined time. Is started to reduce the data access time.

4 is an operation timing diagram of FIG. A description with reference to FIG. 4 and FIG.

As shown in FIG. 4, the timing difference of the clock RASB in FIG. 4 is operated by the low address input buffer 70, the predecoder and the low decoder 90 (not shown). According to the present invention, the interval A from the polling edge of the clock RASB to the generation of the signal PXi can be reduced, so that the time tRAC and tCSH can be reduced, thereby enabling fast data access.

Although the present invention described above is limited to, for example, the drawings, the same will be apparent to those skilled in the art that various changes and modifications can be made without departing from the technical spirit of the present invention.

Claims (3)

Buffering the low address strobe clock from the outside of the chip to the low address strobe buffer and inputting an address signal from the outside of the chip to the low address input buffer to input the low address strobe buffer. A method of fast data access in a semiconductor memory device comprising buffering by a control signal and activating a word line by decoding the buffered address signal through a low decoder and a secondary decoder. A first process of inputting an address strobe clock to a low address strobe buffer at a logic high state and outputting a low address input control signal to the low address input buffer; and performing the low address when the low address strobe clock is logic high A second process of outputting a low address buffered by the low decoder and the first control signal generator after a predetermined time by a right address input control signal, and in a period in which the low address strobe clock is in a logic high state, the low address A third process of outputting a decoded low address by the low decoder performing a decoding operation in response to the low addresses generated in an input buffer, and the low address strobe clock is logic low after a predetermined time of the third process operation. A fourth process of generating the second control signal by the low address strobe buffer when the state is set, and by the first control signal generator controlled by the second control signal after a predetermined time of operation of the fourth process. A fifth process of decoding low addresses and outputting a first control signal, and the low decoder and the first agent Signal Generators The decoded row address and a first and a word line driver operation by means of the control signal high-speed data access method of a semiconductor memory device, characterized by a sixth step of selecting the word line in the output. The semiconductor of claim 1, wherein the first process operates the low address input control signal as a pulse to operate the low address input buffer only within the pulse period, thereby inputting the low address into the chip. Fast data access method of memory device. 2. The method of claim 1, wherein the first process outputs the low address input control signal at all times when the low address strobe clock is in a logic high state so that the low address input buffer always receives an address in the interval. A high speed data access method of a semiconductor memory device.