KR19980027932A - Automatic precharge bank select circuit - Google Patents

Abstract

An automatic precharge bank selection circuit is disclosed in which a precharge is not performed for a corresponding bank when a semiconductor memory device continuously accesses the same bank. The automatic precharge bank selection circuit is a synchronous semiconductor memory device including a plurality of memory banks. The automatic precharge is activated when a signal (COSAP) and an automatic precharge command are applied when a row address is input. A precharge signal generation unit for ANDing and outputting a command signal; A bank decoder for decoding and outputting a bank address applied from the outside; A control transmitter configured to transmit an output of the bank decoder when an output of the precharge signal generator is active; A delay transmitter for delayed transmission of the output of the control transmitter in synchronization with a clock; And determining whether a bank address is changed by comparing the output of the delay transmitter with the output of the bank decoder. When a bank address is changed, a signal for precharging the selected bank according to the output of the delay transmitter is generated. If is not changed, it includes an output logic section for generating a signal to prevent any bank from being precharged. The automatic precharge bank selection circuit has an advantage in that the operation speed increases because the precharge operation is not performed when the row address operation for the same bank is performed.

Description

Automatic precharge bank select circuit

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to semiconductor memory devices, and more particularly, to an automatic precharge bank selection circuit that precharges a row chain in a synchronous semiconductor memory device.

The synchronous semiconductor memory device developed for ultra-fast operation speed performs all operations necessary for data reading and writing in synchronization with a clock PCLK of a predetermined period supplied from the outside. In addition, the synchronous semiconductor memory device includes a mode set register programmed by an external signal, and the latency and the burst length are determined according to the contents of the programmed mode set register. Latency is the number of pulses of the clock output from the input of the external control signal, and burst length is the number of bits of data to be output.

In the semiconductor memory device, as an indispensable operation, a column chain that has been activated must be precharged to perform a read and write operation of one row. The method of precharging a column chain includes a method of precharging only a column chain of a bank selected by a separate command and a method of automatically precharging a column chain requiring precharging. An automatic precharge bank selection circuit can occupy.

1 is a diagram illustrating an automatic precharge bank selection circuit according to the related art, and includes a bank decoder 120, a control transmitter 150, a precharge signal generator 110, a delay transmitter 160, and an output unit. And 200. The bank decoder 120 includes inverters 121, 122, 141, 142, 143, and 144 and NAND gates 131, 132, 133, and 134, and decodes and outputs bank addresses CA12 and CA13. . The precharge signal generator 110 includes a NAND gate 111 and an inverter 112. The precharge signal generator 110 is activated when a COSAP signal and an automatic precharge command are activated when a row address is input. The command signal CA10 is ANDed and output. The control transmitter 150 includes NAND gates 151, 152, 153, and 154, and each of the NAND gates 151, 152, 153, and 154 corresponds to one of the outputs of the bank decoder 120, respectively. A logic NAND operation is performed on the output and the output of the precharge signal generator 110. Therefore, only those corresponding to the selected bank among the outputs of the NAND gates 151, 152, 153, and 154 are low level (low active), and the others are high level. The delay transmitter 160 may include transmission gates 171, 172, 173, 174, inverters 161, 162, 163, 181, 182, 183, 184, 185, 186, 187, 188, and NAND gates ( 191, 192, 193, and 194). When the clock is at the low level, the transfer gates are turned on so that the output of the NAND gates 151, 152, 153, 154 is transmitted. The NAND gates 191, 192, 193, and 194 respectively input a clock PCLK and an output of the inverters 181, 183, 185, and 187 to perform a logic NAND operation. Thus, the delay transmitter 160 has only the signal corresponding to the selected bank is at the low level, and the rest is at the high level. The output unit 200 is composed of inverters 201, 202, 203, 204, 211, 212, 213, 214. 2 are timing diagrams for describing an operation of the automatic precharge bank selection circuit shown in FIG. 1. Referring to this, the clock PCLK is generated when the system clock SCK applied from the outside of the semiconductor memory device is delayed for a predetermined period, and a read and write operation is performed in the semiconductor memory device based on this. The CSB is a chip select signal, the RASB low address strobe signal, the CASB is a column address strobe signal, and the WEB is a write enable signal, all of which are low level active. B-ADD denotes an address, and B and A in the timing waveform indicate that a corresponding bank address is applied. A10 indicates a signal applied to the address pin 10. In FIG. 2, when CASB is active at a low level, A10 is applied at a high level. The COSAP is an active signal when the input of the row address is completed. In the T1 period, the write operation is performed for the bank B, in the T2 period, the gapless write operation is performed for the bank A, and in the T3 period, the gapless write operation is performed for the bank A successively. There is a gap for one pulse period, and a write operation for bank A is performed in a period T4.

However, as shown in Fig. 2, the automatic precharge bank selection circuit performs precharge even when the same bank is continuously accessed without gaps. Thus, even when performing row addresses for the same bank, a separate column address operation is required, which reduces the operation speed.

Accordingly, it is an object of the present invention to provide an automatic precharge bank selection circuit that does not perform precharge for the same bank when continuously accessing the same bank.

Another object of the present invention is to provide an automatic precharge bank selection circuit which does not need to perform a separate column address operation when continuously accessing the same bank.

1 is a circuit diagram of an automatic precharge bank selection circuit according to the prior art.

FIG. 2 is a timing diagram for describing an operation of the automatic precharge bank selection circuit shown in FIG. 1.

3 is a block diagram illustrating an automatic precharge bank selection circuit according to an embodiment of the present invention.

4 is a block diagram illustrating an automatic precharge bank selection circuit according to another embodiment of the present invention.

FIG. 5 illustrates an embodiment of an output logic unit in the automatic precharge bank selection circuit shown in FIGS. 3 and 4.

6 is a detailed circuit diagram of an automatic precharge bank selection circuit according to another embodiment of the present invention.

7 is a timing diagram for explaining the operation of the automatic precharge bank selection circuit shown in FIG.

<Explanation of symbols for main parts of drawing>

110 ... precharge signal generator 120 ... bank decoder

150 ... control transmitter 160 ... delay transmitter

300 ... output logic 310 ... clock input

In order to achieve the above object, the automatic precharge bank selection circuit according to the present invention is a synchronous semiconductor memory device including a plurality of memory banks, wherein the signal COSAP and the automatic precharge that are activated when the input of the row address is completed are completed. A precharge signal generator for performing an AND operation on the active automatic precharge command signal when the command is applied; A bank decoder for decoding and outputting a bank address applied from the outside; A control transmitter configured to transmit an output of the bank decoder when an output of the precharge signal generator is active; A delay transmitter for delayed transmission of the output of the control transmitter in synchronization with a clock; And determining whether a bank address is changed by comparing the output of the delay transmitter with the output of the bank decoder. If is not changed, it includes an output logic section for generating a signal so that no bank is precharged.

Next, the present invention will be described in detail with reference to the accompanying drawings.

3 is a block diagram illustrating an automatic precharge bank selection circuit according to an embodiment of the present invention. In FIG. 3, the automatic precharge bank selection circuit includes a bank decoder 120, a precharge signal generator 110, a control transmitter 150, a delay transmitter 160, and an output logic unit 300. It is composed.

The bank decoder 120 decodes and outputs the bank addresses CA12 and CA13, and the precharge signal generator 110 automatically activates the signal COSAP that is activated at the time when the input of the row address is completed and from the outside. When the automatic precharge command signal CA10 that is activated when applied to the command is all active, the activated signal is output. The control transmitter 150 transmits the output of the bank decoder 120 when the output of the precharge signal generator 110 is active. The delay transmitter 160 delays the output of the control transmitter 150 in synchronization with a clock. The output logic unit 300 may output corresponding outputs among the outputs Y0, Y1, Y2, and Y3 of the delay transmitter 160 and the outputs X0, X1, X2, and X3 of the bank decoder 120. By comparing, it is determined whether or not the bank address is changed. When the bank address is changed, a signal is generated to precharge the selected bank according to the outputs Y0, Y1, Y2, and Y3 of the delay transmission unit 160, and the bank address is changed. If is not changed, a signal is generated so that neither bank is precharged.

4 is a block diagram illustrating an automatic precharge bank selection circuit according to another embodiment of the present invention, and further includes a clock input unit 310. The clock input unit delays the clock in consideration of signal delays caused by the bank decoder 120, the control transmitter 150, and the like during the configuration of the automatic precharge bank selection circuit.

FIG. 5 is a circuit diagram illustrating an embodiment of the output logic unit 300 shown in FIGS. 3 and 4, and includes inverters 321, 322, 323, 324, 341, 342, 343, and 344 and NAND gates 331. , 332, 333, 334. In particular, the output of the bank decoder 120 and the output of the delay transmitter 160 are high active, and the output logic unit 300 is configured to be low active. In this case, the output of the bank decoder 120, the output of the delay transmitter 160, and the output of the output logic unit 300 are as shown in Tables 1, 2, and 3, respectively.

CA12 CA13 X0 X1 X2 X3 0 0 One 0 0 0 0 One 0 0 One 0 One 0 0 One 0 0 One One 0 0 0 One

Output of the bank decoder 120 (if high active) CA12 CA13 X0 X1 X2 X3 0 0 One 0 0 0 0 One 0 0 One 0 One 0 0 One 0 0 One One 0 0 0 One

Output of delay transmitter 160 (if active) Current CA12 Current CA13 CA12 CA13 PAPB_A PAPB_B PAPB_C PAPB_D 0 0 0 0 One One One One 0 0 0 One 0 One One One 0 0 One 0 0 One One One 0 0 One One 0 One One One 0 One 0 0 One One 0 One 0 One 0 One One One One One 0 One One 0 One One 0 One 0 One One One One One 0 One One 0 0 0 One 0 One One One 0 0 One One 0 One One One 0 One 0 One One One One One 0 One One One 0 One One One One 0 0 One One One 0 One One 0 One One One One 0 One One One 0 One One One 0 One One One One One One One One

Output Characteristic Table of Output Logic Unit 300 (when Low Active) FIG. 6 illustrates an automatic precharge bank selection circuit in accordance with another embodiment of the present invention. In FIG. 6, the automatic precharge bank selection circuit includes a bank decoder 120, a delay capacitor 350, a precharge signal generator 110, a control transmitter 150, a delay transmitter 160, and a clock input unit. And an output logic unit 340. The delay capacitor unit 350 includes P-type MOS capacitors 351, 352, 353, and 354 connected between the output terminal of the bank decoder unit 120 and the power supply voltage, and the output terminal and the ground voltage of the bank decoder unit 120. N-type MOS capacitors 361, 362, 363, and 364 are connected to each other. The bank decoder 120 includes inverters 121, 122, 141, 142, 143, and 144 and NAND gates 131, 132, 133, and 134, and decodes the bank addresses CA12 and CA13. To print. Table 4 shows output characteristics of the NAND gates 131, 132, 133, and 134.

CA12 CA13 Print NAND gate (131) NAND gate (132) NAND gate (133) NAND Gate (134) 0 0 0 One One One 0 One One One 0 One One 0 One 0 One One One One One One One 0

As can be seen in Table 4, the output of the NAND gates 131, 132, 133, and 134 is the low level of the output of only one NAND gate corresponding to the selected bank, and the output of the remaining NAND gates is the high level. Becomes Accordingly, the outputs of the inverters 141, 142, 143, and 144 are only at the high level of the output of the inverter corresponding to the selected bank. The precharge signal generator 110 includes a NAND gate 111 and an inverter 112. When the COSAP signal and the automatic precharge command are applied when the row address is input, the precharge signal generator 110 is automatically activated. The precharge command signal CA10 is ANDed and output. The P-type MOS capacitors 351, 352, 353, and 354 and the N-type MOS capacitors 361, 362, 363, and 364 constituting the delay capacitor unit 350 are for delaying a signal. The NAND gates 151, 152, 153, and 154 constituting the control transmitter 150 are logical NAND with respect to any one of the outputs of the bank decoder 120 and the output of the precharge signal generator 110. Perform the operation and output it. Therefore, when the COSAP signal and the auto precharge command signal CA10 are both at the high level, the output corresponding to the bank selected from among the outputs of the NAND gates 151, 152, 153, and 154 is at a low level and the rest is High level. On the other hand, when one of the COSAP signal and the auto precharge command signal CA10 is at a low level, the outputs of the NAND gates 151, 152, 153, and 154 are all at a high level.

The delay transmitter 160 may include an inverter 161 that inverts the output of the clock input unit 310, an inverter 162 that inverts the output of the inverter 161, transmission gates 171, 172, 173, and 174 and a latch. And inverters 181, 182, 183, 184, 185, 186, 187, and 188, and NAND gates 191, 192, 193, and 194. Each of the transmission gates 171, 172, 173, and 174 transmits outputs of the NAND gates 151, 152, 153, and 154 when the output of the clock input 310 is at a low level. Latches made up of inverters 181, 182, 183, 184, 185, 186, 187, 188 maintain the output of the corresponding transfer gates while the corresponding transfer gates are off. The NAND gates 191, 192, 193, and 194 perform logical NAND operations on any one of the outputs of the inverters 181, 183, 185, and 187 and the output of the clock input unit 310, respectively. Thus, the output of the NAND gates is shown in Table 5 below. The output logic unit 300 is composed of inverters 371, 372, 373, and 374 and NAND gates 341, 342, 343, and 344. The precharge bank select signals PAPB_A, PAPB_B, PAPB_C, and PAPB_D) exhibit the characteristics shown in Table 6 below.

CA12 CA13 PCLK = 0 PCLK = 1 NAND gate (191) NAND Gate (192) NAND Gate (193) NAND gate (194) NAND gate (191) NAND Gate (192) NAND Gate (193) NAND gate (194) 0 0 One One One One 0 One One One 0 One One One One One One One 0 One One 0 One One One One One 0 One One One One One One One One One One One 0

Output Characteristics of Delayed Transmitter 160 CA12 CA13 Current CA12 Current CA13 PCLK = 0 PCLK = 1 PAPB_A PAPB_B PAPB_C PAPB_D PAPB_A PAPB_B PAPB_C PAPB_D 0 0 0 0 One One One One One One One One 0 0 0 One One One One One 0 One One One 0 0 One 0 One One One One 0 One One One 0 0 One One One One One One 0 One One One 0 One 0 0 One One One One One One 0 One 0 One 0 One One One One One One One One One 0 One One 0 One One One One One One 0 One 0 One One One One One One One One One 0 One One 0 0 0 One One One One One 0 One One One 0 0 One One One One One One 0 One One One 0 One 0 One One One One One One One One One 0 One One One One One One One 0 One One One One 0 0 One One One One One One One 0 One One 0 One One One One One One One One 0 One One One 0 One One One One One One One 0 One One One One One One One One One One One One

Output Characteristic Table (COSAP = 1, CA10 = 1) As can be seen in Table 6 above, the final output of the automatic precharge bank selection circuit outputs a low active signal by decoding the previous bank address, If the bank address is the same as the current bank address, no precharge is performed. As a result, when the output of the precharge signal generator 110 is active and the bank address is changed, the selected bank is automatically precharged, and precharge is not performed during the period where the bank address is not changed.

However, when continuously accessing the same bank for a long period of time, it is necessary to precharge with a predetermined period, but such a function can be implemented through a separate circuit.

FIG. 7 is a timing diagram for describing an operation of the automatic precharge bank selection circuit shown in FIG. 6, and reference numeral B-ADD denotes a time point at which bank addresses CA12 and CA13 are applied. When the column address strobe signal CASB is active at a low level, an automatic precharge command signal CA10 is generated according to a signal applied to the address pin A10. The COSAP signal performs a write operation on a selected bank. In this case it is an active signal. In the T1 period, a write operation is performed for the bank B, in the T2 period, a gapless write operation is performed for the bank A, and in the T3 period, a gapless write operation is performed for the bank A successively. There is a gap for one pulse period, and a write operation for bank A is performed in a period T4. As can be seen from the figure, in the automatic precharge bank selection circuit according to the present invention, when the gapless access to the same bank is performed, the automatic precharge operation is not performed. (PAPB_A and FIG. 3 in FIG. The above embodiment has been described based on the write operation, but can also be applied to the read operation. In addition, the present invention is not limited to the above embodiment and can be easily modified by those skilled in the art of semiconductor memory devices.

As can be seen from the above, the automatic precharge bank selection circuit according to the present invention does not perform the precharge operation when the same bank is gaplessly accessed and a read or write operation is performed. A precharge operation is performed for the selected bank. Therefore, there is an advantage that the operation speed is increased by not performing an unnecessary precharge operation.

Claims (5)

In a synchronous semiconductor memory device including a plurality of memory banks, A precharge signal generation unit configured to perform an AND operation on the active COSAP signal and an automatic precharge command signal that is activated when the row address input is completed; A bank decoder for decoding and outputting a bank address applied from the outside; A control transmitter configured to transmit an output of the bank decoder when an output of the precharge signal generator is active; A delay transmitter for delayed transmission of the output of the control transmitter in synchronization with a clock; And By comparing the output of the delay transmitter with the output of the bank decoder, it is determined whether a bank address is changed. When a bank address is changed, a signal for precharging the selected bank according to the output of the delay transmitter is generated. And an output logic section for generating a signal to prevent any bank from being precharged if it is not changed. 2. The semiconductor memory device of claim 1, further comprising: P-type MOS capacitors each having a gate connected to outputs of the bank decoder unit, and a source and a drain thereof commonly connected to a power supply voltage; And And n-type MOS capacitors each having a gate connected to the outputs of the bank decoder unit, and having a source and a drain thereof commonly connected to a ground voltage. 2. The apparatus of claim 1, further comprising: a first inverter for inverting the clock; A P-type MOS capacitor having a gate connected to an output of the first inverter and a source and a drain thereof commonly connected to a power supply voltage; An N-type MOS capacitor having a gate connected to an output of the first inverter, and a source and a drain thereof commonly connected to a ground voltage; And And a second inverter for inverting the output of the first inverter, wherein the output of the second inverter is applied to the delay transmitter as a clock. The method of claim 1, wherein the bank decoder is A plurality of first NAND gates, wherein only one of the first NAND gates indicates a low level according to the bank address; And And a plurality of first inverters for inverting the output of the NAND gates. The method of claim 4, wherein the output logic unit A plurality of second inverters for inverting outputs of the delay transmitter; And And a plurality of second NAND gates configured to perform a logic NAND operation on the outputs of the first NAND gates and corresponding ones of the outputs of the second inverters. .